Datasheet SLG46811 (Dialog Semiconductor)
| Manufacturer | Dialog Semiconductor |
| Description | GreenPAK Programmable Mixed-signal Matrix |
| Pages / Page | 168 / 1 — SLG46811. GreenPAK Programmable Mixed-Signal Matrix. Preliminary. General … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
SLG46811. GreenPAK Programmable Mixed-Signal Matrix. Preliminary. General Description. Key Features. Applications. Datasheet
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SLG46811 GreenPAK Programmable Mixed-Signal Matrix Preliminary General Description
The SLG46811 provides a small, low power component for commonly used Mixed-Signal functions. The user creates their circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the interconnect logic, the IO Pins, and the macrocells of the SLG46811. This highly versatile device allows a wide variety of Mixed-Signal functions to be designed within a very small, low power single integrated circuit.
Key Features
Multichannel Sampling Analog Comparator (MS ACMP) Two Oscillators (OSC) Sampling up to Four Analog Channels Selectable 2.048 kHz or 10 kHz Oscillator Selectable Voltage Reference for Each Channel 25 MHz Oscillator Different Sampling Scenarios Analog Temperature Sensor Synchronous or Asynchronous Result Appearance Power-On Reset (POR) with CRC Integrated Voltage References (Vref) Read Back Protection (Read Lock) Twelve Combination Function Macrocells Power Supply Two 2-Bit LUT or DFF/LATCH Macrocells 2.3 V ≤ VDD ≤ 5.5 V One Selectable Programmable Pattern Generator or 2- Operating Temperature Range: -40 °C to 85 °C bit LUT RoHS Compliant/Halogen-Free Four 3-Bit LUT or DFF/LATCH with Set/Reset Available Package Four Selectable DFF/LATCH or 3-bit LUTs or Shift 12-pin STQFN: 1.6 mm x 1.6 mm x 0.55 mm, 0.4 mm Registers pitch One 4-Bit LUT or DFF/LATCH with Set/Reset Macro- cell Six Multi-Function Macrocells Five Selectable DFF/LATCH or 3-bit LUTs + 8-bit Delay/Counters One Selectable DFF/LATCH or 3-bit LUTs + 8-bit Delay/Counter/FSM Extended Pattern Generator Up to 8 Parallel Outputs 92 bytes Pattern Stored in the NVM Serial Communications I2C Protocol Interface Programmable Delay with Edge Detector Output Deglitch Filter or Edge Detector
Applications
Notebook and Tablet PCs Smartphones and Fitness Bands Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics
Datasheet Revision 2.2 3-Feb-2021
CFR0011-120-00 1 of 168 © 2021 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 12 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 I2C Pins Electrical Characteristics 3.6 Macrocells Current Consumption 3.7 Timing Characteristics 3.8 Counter/Delay Characteristics 3.9 Oscillator Characteristics 3.9.1 OSC Power-On Delay 3.10 MS ACMP Characteristics 3.11 Analog Temperature Sensor Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-up/down during Power-up 5.5 GPI Structure 5.5.1 GPI Structure (for GPI) 5.6 GPIO with I2C Mode IO Structure 5.6.1 GPIO with I2C Mode Structure (for GPIO0 and GPIO1) 5.7 Matrix OE IO Structure 5.7.1 Matrix OE IO Structure (for GPIO2, GPIO3, GPIO7, GPIO8) 5.8 Register OE IO Structure 5.8.1 Register OE IO Structure (for GPIO4, GPIO5, GPIO6) 5.9 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.2 2-bit LUT or Programmable Pattern Generator 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells Or Shift Register Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.4 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.5 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.5.1 4-Bit LUT Macrocell Used as 4-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY5 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY5 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY5 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY5 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY5 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY5 8.2.7 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 FSM Timing Diagrams 9 Multichannel Sampling Analog Comparator 9.1 Multichannel Sampling ACMP Block Diagram 9.2 MS ACMP Timing Diagrams 9.3 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 13 Clocking 13.1 OSC General description 13.2 Oscillator0 (2.048 kHz/10 kHz) 13.3 Oscillator1 (25 MHz) 13.4 CNT/DLY Clock Scheme 13.5 External Clocking 13.5.1 GPI Source for Oscillator0 (2.048kHz/10 kHz) 13.5.2 GPIO Source for Oscillator1 (25 MHz) 13.6 Oscillators Power-On Delay 13.7 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 I2C Serial Command Register Map 15.6 I2C Additional Options 15.6.1 I2C Byte Write Bit Masking 16 Extended Pattern Generator 17 Analog Temperature Sensor 18 Register Definitions 18.1 Register Map 19 Package Top Marking Definitions 19.1 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, before February 1, 2021 19.2 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, after February 1, 2021 20 Package Information 20.1 Package outlines FOR STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package 20.2 Moisture Sensitivity Level 20.3 Soldering Information 21 Ordering Information 21.1 Tape and Reel Specifications 21.2 Carrier Tape Drawing and Dimensions 22 Layout Guidelines 22.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package Glossary Revision History
The SLG46811 provides a small, low power component for commonly used Mixed-Signal functions. The user creates their circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the interconnect logic, the IO Pins, and the macrocells of the SLG46811. This highly versatile device allows a wide variety of Mixed-Signal functions to be designed within a very small, low power single integrated circuit.
Key Features
Multichannel Sampling Analog Comparator (MS ACMP) Two Oscillators (OSC) Sampling up to Four Analog Channels Selectable 2.048 kHz or 10 kHz Oscillator Selectable Voltage Reference for Each Channel 25 MHz Oscillator Different Sampling Scenarios Analog Temperature Sensor Synchronous or Asynchronous Result Appearance Power-On Reset (POR) with CRC Integrated Voltage References (Vref) Read Back Protection (Read Lock) Twelve Combination Function Macrocells Power Supply Two 2-Bit LUT or DFF/LATCH Macrocells 2.3 V ≤ VDD ≤ 5.5 V One Selectable Programmable Pattern Generator or 2- Operating Temperature Range: -40 °C to 85 °C bit LUT RoHS Compliant/Halogen-Free Four 3-Bit LUT or DFF/LATCH with Set/Reset Available Package Four Selectable DFF/LATCH or 3-bit LUTs or Shift 12-pin STQFN: 1.6 mm x 1.6 mm x 0.55 mm, 0.4 mm Registers pitch One 4-Bit LUT or DFF/LATCH with Set/Reset Macro- cell Six Multi-Function Macrocells Five Selectable DFF/LATCH or 3-bit LUTs + 8-bit Delay/Counters One Selectable DFF/LATCH or 3-bit LUTs + 8-bit Delay/Counter/FSM Extended Pattern Generator Up to 8 Parallel Outputs 92 bytes Pattern Stored in the NVM Serial Communications I2C Protocol Interface Programmable Delay with Edge Detector Output Deglitch Filter or Edge Detector
Applications
Notebook and Tablet PCs Smartphones and Fitness Bands Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics
Datasheet Revision 2.2 3-Feb-2021
CFR0011-120-00 1 of 168 © 2021 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 12 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 I2C Pins Electrical Characteristics 3.6 Macrocells Current Consumption 3.7 Timing Characteristics 3.8 Counter/Delay Characteristics 3.9 Oscillator Characteristics 3.9.1 OSC Power-On Delay 3.10 MS ACMP Characteristics 3.11 Analog Temperature Sensor Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-up/down during Power-up 5.5 GPI Structure 5.5.1 GPI Structure (for GPI) 5.6 GPIO with I2C Mode IO Structure 5.6.1 GPIO with I2C Mode Structure (for GPIO0 and GPIO1) 5.7 Matrix OE IO Structure 5.7.1 Matrix OE IO Structure (for GPIO2, GPIO3, GPIO7, GPIO8) 5.8 Register OE IO Structure 5.8.1 Register OE IO Structure (for GPIO4, GPIO5, GPIO6) 5.9 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.2 2-bit LUT or Programmable Pattern Generator 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells Or Shift Register Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.4 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.5 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.5.1 4-Bit LUT Macrocell Used as 4-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY5 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY5 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY5 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY5 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY5 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY5 8.2.7 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 FSM Timing Diagrams 9 Multichannel Sampling Analog Comparator 9.1 Multichannel Sampling ACMP Block Diagram 9.2 MS ACMP Timing Diagrams 9.3 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 13 Clocking 13.1 OSC General description 13.2 Oscillator0 (2.048 kHz/10 kHz) 13.3 Oscillator1 (25 MHz) 13.4 CNT/DLY Clock Scheme 13.5 External Clocking 13.5.1 GPI Source for Oscillator0 (2.048kHz/10 kHz) 13.5.2 GPIO Source for Oscillator1 (25 MHz) 13.6 Oscillators Power-On Delay 13.7 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 I2C Serial Command Register Map 15.6 I2C Additional Options 15.6.1 I2C Byte Write Bit Masking 16 Extended Pattern Generator 17 Analog Temperature Sensor 18 Register Definitions 18.1 Register Map 19 Package Top Marking Definitions 19.1 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, before February 1, 2021 19.2 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, after February 1, 2021 20 Package Information 20.1 Package outlines FOR STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package 20.2 Moisture Sensitivity Level 20.3 Soldering Information 21 Ordering Information 21.1 Tape and Reel Specifications 21.2 Carrier Tape Drawing and Dimensions 22 Layout Guidelines 22.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package Glossary Revision History
