Datasheet LM73100 (Texas Instruments) - 7

LM7310 www.ti.com
SNOSDC0A – OCTOBER 2020 – REVISED DECEMBER 2020
6.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, VEN/UVLO = 2 V, VOVLO = 0 V, dVdT = Open, RIMON = 549 Ω, PGTH = Open, PG = Open, OUT = Open. All voltages referenced to GND.
Test Description MIN TYP MAX UNITS Parameter POWER GOOD INDICATION (PG)
PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < 0.67 0.9 V VSD, IPG = 26 µA VPGD PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < 0.78 1 V VSD, IPG = 242 µA PG pin low voltage while de-asserted, VIN > VUVP(R) 0.6 V IPGLKG PG pin leakage current while asserted 0.5 2 µA
POWERGOOD THRESHOLD (PGTH)
VPGTH(R) PGTH rising threshold 1.183 1.2 1.223 V VPGTH(F) PGTH falling threshold 1.076 1.09 1.116 V IPGTHLKG PGTH leakage current –1 1 µA
OVERTEMPERATURE PROTECTION (OTP)
TSD Thermal shutdown rising threshold, TJ↑ 154 °C TSDHYS Thermal shutdown hysteresis, TJ↓ 10 °C
DVDT
IdVdt dVdt pin charging current 1.15 2.34 3.66 µA
6.6 Timing Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tOVLO Overvoltage lock-out response time VOVLO > VOV(R) to VOUT↓ 1.1 µs tFT Fixed fast-trip response time IOUT > IFT to IOUT↓ 500 ns tSWRCB Reverse Current Blocking recovery time (VIN - VOUT) > VFWDTH to VOUT ↑ 50 µs Reverse Current Blocking fast comparator tRCB (V response time OUT - VIN) > 1.3 x VREVTH to BFET OFF 1 µs tPGA PG Assertion de-glitch 12 µs tPGD PG De-assertion de-glitch 12 µs Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM7310 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Reverse Polarity Protection 7.3.2 Undervoltage Protection (UVLO & UVP) 7.3.3 Overvoltage Lockout (OVLO) 7.3.4 Inrush Current control and Fast-trip 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control 7.3.4.2 Fast-Trip During Steady State 7.3.5 Analog Load Current Monitor Output 7.3.6 Reverse Current Protection 7.3.7 Overtemperature Protection (OTP) 7.3.8 Fault Response 7.3.9 Power Good Indication (PG) 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Single Device, Self-Controlled 8.2.1 Typical Application 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds 8.2.1.2.2 Setting Output Voltage Rise Time (tR) 8.2.1.2.3 Setting Power Good Assertion Threshold 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range 8.2.1.3 Application Curves 8.3 Active ORing 8.4 Priority Power MUXing 8.5 USB PD Port Protection 8.6 Parallel Operation 9 Power Supply Recommendations 9.1 Transient Protection 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information