Datasheet SiC450, SiC451, SiC453 (Vishay) - 9
| Manufacturer | Vishay |
| Description | 4.5 V to 20 V Input, 15 A, 25 A, 40 A microBuck DC/DC Converter With PMBus Interface |
| Pages / Page | 48 / 9 — SiC450, SiC451, SiC453. Input-Overvoltage Protection (VIN-OVP). … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
SiC450, SiC451, SiC453. Input-Overvoltage Protection (VIN-OVP). Input-Undervoltage Protection (VIN-UVP)
Model Line for this Datasheet
Text Version of Document
SiC450, SiC451, SiC453
www.vishay.com Vishay Siliconix
Input-Overvoltage Protection (VIN-OVP)
VIN-OVP is implemented by monitoring the input voltage. When the input voltage is pulled above a threshold voltage VIN_OV_FAULT_LIMIT (VIN-OFL), the input-overvoltage (VIN-OV) fault condition is recognized and both the HS and LS MOSFETs are turned off. When the input voltage is pulled below the VIN-OFL, the VIN-OV fault condition no longer exists and the device restarts. The VIN-OFL can be programmed via PMBus (see PMBus command section). The default value of VIN-OFL is 15 V. The VIN-OVP is enabled immediately after VDD passes UVLO level.
Input-Undervoltage Protection (VIN-UVP) Fig. 8 - Pre-Bias Start-Up
VIN-UVP is implemented by monitoring the input voltage. When the input voltage is pulled below a threshold V
Output Voltage Setting
IN_OFF, the input-undervoltage (VIN-UV) fault condition is recognized Connecting a resistor from VSET to AGND will set output and both the HS and LS MOSFETs are turned off. When the voltage (VOUT), eight VOUT related warning and fault voltage input voltage is pulled above a threshold VIN_ON, the VIN-UV limits, and the value of VOUT_SCALE_LOOP as listed in the fault condition no longer exists and the device restarts. “VOUT_SCALE_LOOP look up” table. See below table for The V the list of supported output voltage (V IN-OFF and VIN_ON can be programmed via PMBus (see OUT) set by the VSET PMBus command section). The default value of V resistor value. After V IN-OFF is OUT is set by the resistor, the voltage 9 V. The default value of V level of eight V IN_ON is 10 V. OUT related warning and fault limits defined by PMBus and the VOUT_SCALE_LOOP register are The VIN-UVP is enabled immediately after VDD passes UVLO automatically set also. See below table for the list of the level. eight VOUT related warning and fault limits set by VOUT
tON-MAX. Protection (tMP)
setting resistor. Please do not leave the setting resistor open SiC45x has power up time limit control. When the device or short, or contact Vishay for technical support. The resistor does not power up the output voltage above the V setting V UFL in a OUT or anyone of the eight VOUT related warning and time interval longer than t fault limits can be separately overridden by a PMBus ON_MAX_FAULT_LIMIT (tMFL), the t command with resolution 1.953 mV (see PMBus command ON-MAX. (tM) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device continues table). restart attempt after the shutdown in a delay time until the tM fault no longer exists.
OUTPUT VOLTAGE SETTINGS
The tMFL and delay time can be programmed via PMBus (see PMBus command section). The default value of t
VSET RESISTOR (k
Ω
) VOUT (V)
MFL is 20 ms. The default delay time is 20 ms. 0.845 0.60 The t 1.30 0.90 MP is enabled immediately after VDD passes UVLO level. 1.78 0.95
Overtemperature Protection (OTP)
2.32 1.00 SiC45x has internal thermal monitor block to support device 2.87 1.05 temperature control. When the device temperature rises 3.48 1.20 above OT_FAULT_LIMIT (OFL), the overtemperature (OT) fault condition is recognized and both the HS and LS 4.12 1.25 MOSFETs are turned off. When OT fault condition no longer 4.75 1.50 exists, the device restarts. 5.49 1.80 The OFL can be programmed via PMBus (see PMBus 6.19 2.10 command section). The default value of OFL is 125 °C. 6.98 2.50 The OTP is enabled immediately after V 7.87 3.30 DD passes UVLO level. 8.87 5.00 11.0 12.00
Pre-Bias Start-Up
VOUT is monitored through differential output voltage sense pins Vsen+ and Vsen-. If the sensed voltage is higher than VSET, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. S21-0213-Rev. B, 08-Mar-2021
9
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
Input-Overvoltage Protection (VIN-OVP)
VIN-OVP is implemented by monitoring the input voltage. When the input voltage is pulled above a threshold voltage VIN_OV_FAULT_LIMIT (VIN-OFL), the input-overvoltage (VIN-OV) fault condition is recognized and both the HS and LS MOSFETs are turned off. When the input voltage is pulled below the VIN-OFL, the VIN-OV fault condition no longer exists and the device restarts. The VIN-OFL can be programmed via PMBus (see PMBus command section). The default value of VIN-OFL is 15 V. The VIN-OVP is enabled immediately after VDD passes UVLO level.
Input-Undervoltage Protection (VIN-UVP) Fig. 8 - Pre-Bias Start-Up
VIN-UVP is implemented by monitoring the input voltage. When the input voltage is pulled below a threshold V
Output Voltage Setting
IN_OFF, the input-undervoltage (VIN-UV) fault condition is recognized Connecting a resistor from VSET to AGND will set output and both the HS and LS MOSFETs are turned off. When the voltage (VOUT), eight VOUT related warning and fault voltage input voltage is pulled above a threshold VIN_ON, the VIN-UV limits, and the value of VOUT_SCALE_LOOP as listed in the fault condition no longer exists and the device restarts. “VOUT_SCALE_LOOP look up” table. See below table for The V the list of supported output voltage (V IN-OFF and VIN_ON can be programmed via PMBus (see OUT) set by the VSET PMBus command section). The default value of V resistor value. After V IN-OFF is OUT is set by the resistor, the voltage 9 V. The default value of V level of eight V IN_ON is 10 V. OUT related warning and fault limits defined by PMBus and the VOUT_SCALE_LOOP register are The VIN-UVP is enabled immediately after VDD passes UVLO automatically set also. See below table for the list of the level. eight VOUT related warning and fault limits set by VOUT
tON-MAX. Protection (tMP)
setting resistor. Please do not leave the setting resistor open SiC45x has power up time limit control. When the device or short, or contact Vishay for technical support. The resistor does not power up the output voltage above the V setting V UFL in a OUT or anyone of the eight VOUT related warning and time interval longer than t fault limits can be separately overridden by a PMBus ON_MAX_FAULT_LIMIT (tMFL), the t command with resolution 1.953 mV (see PMBus command ON-MAX. (tM) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device continues table). restart attempt after the shutdown in a delay time until the tM fault no longer exists.
OUTPUT VOLTAGE SETTINGS
The tMFL and delay time can be programmed via PMBus (see PMBus command section). The default value of t
VSET RESISTOR (k
Ω
) VOUT (V)
MFL is 20 ms. The default delay time is 20 ms. 0.845 0.60 The t 1.30 0.90 MP is enabled immediately after VDD passes UVLO level. 1.78 0.95
Overtemperature Protection (OTP)
2.32 1.00 SiC45x has internal thermal monitor block to support device 2.87 1.05 temperature control. When the device temperature rises 3.48 1.20 above OT_FAULT_LIMIT (OFL), the overtemperature (OT) fault condition is recognized and both the HS and LS 4.12 1.25 MOSFETs are turned off. When OT fault condition no longer 4.75 1.50 exists, the device restarts. 5.49 1.80 The OFL can be programmed via PMBus (see PMBus 6.19 2.10 command section). The default value of OFL is 125 °C. 6.98 2.50 The OTP is enabled immediately after V 7.87 3.30 DD passes UVLO level. 8.87 5.00 11.0 12.00
Pre-Bias Start-Up
VOUT is monitored through differential output voltage sense pins Vsen+ and Vsen-. If the sensed voltage is higher than VSET, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. S21-0213-Rev. B, 08-Mar-2021
9
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
