Datasheet MASTERGAN4 (STMicroelectronics) - 5
| Manufacturer | STMicroelectronics |
| Description | High power density 600V half-bridge driver with two enhancement mode GaN HEMT |
| Pages / Page | 27 / 5 — MASTERGAN4. Recommended operating conditions. 3.2. Table 3. Recommended … |
| File Format / Size | PDF / 480 Kb |
| Document Language | English |
MASTERGAN4. Recommended operating conditions. 3.2. Table 3. Recommended operating conditions. Symbol. Parameter. Note. Min Max Unit
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MASTERGAN4 Recommended operating conditions 3.2 Recommended operating conditions Table 3. Recommended operating conditions
Each voltage referred to GND unless otherwise specified
Symbol Parameter Note Min Max Unit
VS High voltage bus - 0 520 V VCC Supply voltage - 4.75 9.5 V - 4.75 6.5 V PVCC-PGND PVCC to PGND Low side supply(1) Best performance 5 6.5 V PVCC Low-side driver supply - 3 8.5 V VCC-PVCC VCC to PVCC pin voltage - -3 3 V PGND Low-side driver ground(1) - -2 2 V DT Suggested minimum dead time - 5 - ns TIN_MIN Minimum duration of input pulse to obtain undistorted output pulse(2) - 120 - ns - 4.4 6.5 V VBO BOOT to OUTb pin voltage(3) Best performance 5 6.5 V BOOT BOOT to GND voltage - 0(4) 530 V Vi Logic inputs voltage range - 0 20 V TJ Junction temperature - -40 125 °C 1. PGND internally connected to SENSE 2. See Section 6.1 Logic inputs for more detail 3. OUTb internally connected to OUT 4. 5 V is recommended during High Side turn-on
3.3 Thermal data Table 4. Thermal data Symbol Parameter Value Unit
Rth(J-CB)_HS Thermal resistance of each transistor’s junction to relevant exposed pad, typical 2.8 °C/W Rth(J-A) Thermal resistance junction-to-ambient(1) 17.8 °C/W The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as per JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation is uniformly distributed over the two GaN transistors.
DS13686
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Rev 1 page 5/27
Document Outline Features Applications Description 1 Block diagram 2 Pin descriptions and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history
MASTERGAN4 Recommended operating conditions 3.2 Recommended operating conditions Table 3. Recommended operating conditions
Each voltage referred to GND unless otherwise specified
Symbol Parameter Note Min Max Unit
VS High voltage bus - 0 520 V VCC Supply voltage - 4.75 9.5 V - 4.75 6.5 V PVCC-PGND PVCC to PGND Low side supply(1) Best performance 5 6.5 V PVCC Low-side driver supply - 3 8.5 V VCC-PVCC VCC to PVCC pin voltage - -3 3 V PGND Low-side driver ground(1) - -2 2 V DT Suggested minimum dead time - 5 - ns TIN_MIN Minimum duration of input pulse to obtain undistorted output pulse(2) - 120 - ns - 4.4 6.5 V VBO BOOT to OUTb pin voltage(3) Best performance 5 6.5 V BOOT BOOT to GND voltage - 0(4) 530 V Vi Logic inputs voltage range - 0 20 V TJ Junction temperature - -40 125 °C 1. PGND internally connected to SENSE 2. See Section 6.1 Logic inputs for more detail 3. OUTb internally connected to OUT 4. 5 V is recommended during High Side turn-on
3.3 Thermal data Table 4. Thermal data Symbol Parameter Value Unit
Rth(J-CB)_HS Thermal resistance of each transistor’s junction to relevant exposed pad, typical 2.8 °C/W Rth(J-A) Thermal resistance junction-to-ambient(1) 17.8 °C/W The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as per JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation is uniformly distributed over the two GaN transistors.
DS13686
-
Rev 1 page 5/27
Document Outline Features Applications Description 1 Block diagram 2 Pin descriptions and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history
