Datasheet AIS2IH (STMicroelectronics) - 10
| Manufacturer | STMicroelectronics |
| Description | MEMS digital output motion sensor: high-performance 3-axis accelerometer for automobile applications |
| Pages / Page | 63 / 10 — AIS2IH. Communication interface characteristics. 2.4.2. I²C - inter-IC … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
AIS2IH. Communication interface characteristics. 2.4.2. I²C - inter-IC control interface. Table 7. I²C slave timing values
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AIS2IH Communication interface characteristics 2.4.2 I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 7. I²C slave timing values I²C fast mode(1)(2) I²C fast mode+(1)(2) I²C high speed mode Symbol Parameter Unit Min. Max. Min. Max. Min. Max
f(SCL) SCL clock frequency 0 400 0 1000 0 3400 kHz tw(SCLL) SCL clock low time 1.3 - 0.5 - 0.16 - µs tw(SCLH) SCL clock high time 0.6 - 0.26 - 0.06 - tsu(SDA) SDA setup time 100 - 50 - 10 - ns th(SDA) SDA data hold time 0.01 0.9 0 - 0 0.07 t START/REPEATED START condition hold h(ST) 0.6 - 0.26 - 0.16 - time tsu(SR) REPEATED START condition setup time 0.6 - 0.26 - 0.16 - t µs su(SP) STOP condition setup time 0.6 - 0.26 - 0.16 - t Bus free time between STOP and START w(SP:SR) 1.3 - 0.5 - - - condition Data valid time - 0.9 - 0.45 - - Data valid acknowledge time - 0.9 - 0.45 - - CB Capacitive load for each bus line - 400 - 550 - 100 pF 1. Data based on standard I²C protocol requirement, not tested in production. 2. Data for I²C fast mode and I²C fast mode+ have been validated by characterization, not tested in production.
Figure 4. I²C slave timing diagram
REPEATED START START tsu(SR) START SDA tw(SP:SR) tsu(SDA) th(SDA) t STOP su(SP) SCL th(ST) tw(SCLL) tw(SCLH) Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS12421
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Rev 4 page 10/63
Document Outline Features Applications Description 1 Block diagram and pin description 1.1 Block diagram 1.2 Pin description 2 Mechanical and electrical specifications 2.1 Mechanical characteristics 2.2 Electrical characteristics 2.3 Temperature sensor characteristics 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface 2.4.2 I²C - inter-IC control interface 2.5 Absolute maximum ratings 3 Terminology and functionality 3.1 Terminology 3.1.1 Sensitivity 3.1.2 Zero-g level offset 3.2 Functionality 3.2.1 Operating modes 3.2.2 Single data conversion on-demand mode 3.2.3 Self-test 3.2.4 Activity/Inactivity, stationary/motion detection functions 3.2.5 High tap/double-tap user configurability 3.2.6 Offset management 3.3 Sensing element 3.4 IC interface 3.5 Factory calibration 3.6 Temperature sensor 4 Application hints 5 Digital main blocks 5.1 Block diagram of filters 5.2 Data stabilization time vs. ODR/device setting 5.3 FIFO 5.3.1 Bypass mode 5.3.2 FIFO mode 5.3.3 Continuous mode 5.3.4 Continuous-to-FIFO mode 5.3.5 Bypass-to-Continuous mode 6 Digital interfaces 6.1 I²C serial interface 6.1.1 I²C operation 6.2 SPI bus interface 6.2.1 SPI read 6.2.2 SPI write 6.2.3 SPI read in 3-wire mode 7 Register mapping 8 Register description 8.1 OUT_T_L (0Dh) 8.2 OUT_T_H (0Eh) 8.3 WHO_AM_I (0Fh) 8.4 CTRL1 (20h) 8.5 CTRL2 (21h) 8.6 CTRL3 (22h) 8.7 CTRL4_INT1_PAD_CTRL (23h) 8.8 CTRL5_INT2_PAD_CTRL (24h) 8.9 CTRL6 (25h) 8.10 OUT_T (26h) 8.11 STATUS (27h) 8.12 OUT_X_L (28h) 8.13 OUT_X_H (29h) 8.14 OUT_Y_L (2Ah) 8.15 OUT_Y_H (2Bh) 8.16 OUT_Z_L (2Ch) 8.17 OUT_Z_H (2Dh) 8.18 FIFO_CTRL (2Eh) 8.19 FIFO_SAMPLES (2Fh) 8.20 TAP_THS_X (30h) 8.21 TAP_THS_Y (31h) 8.22 TAP_THS_Z (32h) 8.23 INT_DUR (33h) 8.24 WAKE_UP_THS (34h) 8.25 WAKE_UP_DUR (35h) 8.26 FREE_FALL (36h) 8.27 STATUS_DUP (37h) 8.28 WAKE_UP_SRC (38h) 8.29 TAP_SRC (39h) 8.30 SIXD_SRC (3Ah) 8.31 ALL_INT_SRC (3Bh) 8.32 X_OFS_USR (3Ch) 8.33 Y_OFS_USR (3Dh) 8.34 Z_OFS_USR (3Eh) 8.35 CTRL7 (3Fh) 9 Package information 9.1 Soldering information 9.2 LGA-12 package information 9.3 LGA-12 packing information Revision history Contents List of tables List of figures
AIS2IH Communication interface characteristics 2.4.2 I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 7. I²C slave timing values I²C fast mode(1)(2) I²C fast mode+(1)(2) I²C high speed mode Symbol Parameter Unit Min. Max. Min. Max. Min. Max
f(SCL) SCL clock frequency 0 400 0 1000 0 3400 kHz tw(SCLL) SCL clock low time 1.3 - 0.5 - 0.16 - µs tw(SCLH) SCL clock high time 0.6 - 0.26 - 0.06 - tsu(SDA) SDA setup time 100 - 50 - 10 - ns th(SDA) SDA data hold time 0.01 0.9 0 - 0 0.07 t START/REPEATED START condition hold h(ST) 0.6 - 0.26 - 0.16 - time tsu(SR) REPEATED START condition setup time 0.6 - 0.26 - 0.16 - t µs su(SP) STOP condition setup time 0.6 - 0.26 - 0.16 - t Bus free time between STOP and START w(SP:SR) 1.3 - 0.5 - - - condition Data valid time - 0.9 - 0.45 - - Data valid acknowledge time - 0.9 - 0.45 - - CB Capacitive load for each bus line - 400 - 550 - 100 pF 1. Data based on standard I²C protocol requirement, not tested in production. 2. Data for I²C fast mode and I²C fast mode+ have been validated by characterization, not tested in production.
Figure 4. I²C slave timing diagram
REPEATED START START tsu(SR) START SDA tw(SP:SR) tsu(SDA) th(SDA) t STOP su(SP) SCL th(ST) tw(SCLL) tw(SCLH) Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS12421
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Rev 4 page 10/63
Document Outline Features Applications Description 1 Block diagram and pin description 1.1 Block diagram 1.2 Pin description 2 Mechanical and electrical specifications 2.1 Mechanical characteristics 2.2 Electrical characteristics 2.3 Temperature sensor characteristics 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface 2.4.2 I²C - inter-IC control interface 2.5 Absolute maximum ratings 3 Terminology and functionality 3.1 Terminology 3.1.1 Sensitivity 3.1.2 Zero-g level offset 3.2 Functionality 3.2.1 Operating modes 3.2.2 Single data conversion on-demand mode 3.2.3 Self-test 3.2.4 Activity/Inactivity, stationary/motion detection functions 3.2.5 High tap/double-tap user configurability 3.2.6 Offset management 3.3 Sensing element 3.4 IC interface 3.5 Factory calibration 3.6 Temperature sensor 4 Application hints 5 Digital main blocks 5.1 Block diagram of filters 5.2 Data stabilization time vs. ODR/device setting 5.3 FIFO 5.3.1 Bypass mode 5.3.2 FIFO mode 5.3.3 Continuous mode 5.3.4 Continuous-to-FIFO mode 5.3.5 Bypass-to-Continuous mode 6 Digital interfaces 6.1 I²C serial interface 6.1.1 I²C operation 6.2 SPI bus interface 6.2.1 SPI read 6.2.2 SPI write 6.2.3 SPI read in 3-wire mode 7 Register mapping 8 Register description 8.1 OUT_T_L (0Dh) 8.2 OUT_T_H (0Eh) 8.3 WHO_AM_I (0Fh) 8.4 CTRL1 (20h) 8.5 CTRL2 (21h) 8.6 CTRL3 (22h) 8.7 CTRL4_INT1_PAD_CTRL (23h) 8.8 CTRL5_INT2_PAD_CTRL (24h) 8.9 CTRL6 (25h) 8.10 OUT_T (26h) 8.11 STATUS (27h) 8.12 OUT_X_L (28h) 8.13 OUT_X_H (29h) 8.14 OUT_Y_L (2Ah) 8.15 OUT_Y_H (2Bh) 8.16 OUT_Z_L (2Ch) 8.17 OUT_Z_H (2Dh) 8.18 FIFO_CTRL (2Eh) 8.19 FIFO_SAMPLES (2Fh) 8.20 TAP_THS_X (30h) 8.21 TAP_THS_Y (31h) 8.22 TAP_THS_Z (32h) 8.23 INT_DUR (33h) 8.24 WAKE_UP_THS (34h) 8.25 WAKE_UP_DUR (35h) 8.26 FREE_FALL (36h) 8.27 STATUS_DUP (37h) 8.28 WAKE_UP_SRC (38h) 8.29 TAP_SRC (39h) 8.30 SIXD_SRC (3Ah) 8.31 ALL_INT_SRC (3Bh) 8.32 X_OFS_USR (3Ch) 8.33 Y_OFS_USR (3Dh) 8.34 Z_OFS_USR (3Eh) 8.35 CTRL7 (3Fh) 9 Package information 9.1 Soldering information 9.2 LGA-12 package information 9.3 LGA-12 packing information Revision history Contents List of tables List of figures
