Datasheet PMN50XP (NXP) - 2
| Manufacturer | NXP |
| Description | P-channel TrenchMOS extremely low level FET |
| Pages / Page | 11 / 2 — NXP Semiconductors. PMN50XP. P-channel TrenchMOS extremely low level FET. … |
| File Format / Size | PDF / 153 Kb |
| Document Language | English |
NXP Semiconductors. PMN50XP. P-channel TrenchMOS extremely low level FET. Pinning information. Table 2. Pinning. Pin. Symbol
Model Line for this Datasheet
Text Version of Document
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NXP Semiconductors PMN50XP P-channel TrenchMOS extremely low level FET 2. Pinning information Table 2. Pinning Pin Symbol Description Simplified outline Graphic Symbol
1 D drain 6 5 4 D 2 D drain 3 G gate 4 S source 1 2 3 G 5 D drain S 6 D drain 003aaa671
3. Ordering information Table 3. Ordering information Type number Package Name Description Version
PMN50XP TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457
4. Limiting values Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V ≥ ≤ DS drain-source voltage Tj 25 °C; Tj 150 °C - -20 V V ≥ ≤ DGR drain-gate voltage Tj 25 °C; Tj 150 °C; RGS = 20 kΩ - -20 V VGS gate-source voltage -12 12 V ID drain current Tsp = 25 °C; VGS = -4.5 V; see Figure 1 and 3 - -4.8 A Tsp = 100 °C; VGS = -4.5 V - -3 A IDM peak drain current Tsp = 25 °C; tp < 10 μs; pulsed; see Figure 3 - -19.4 A Ptot total power dissipation Tsp = 25 °C; see Figure 2 - 2.2 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C
Source-drain diode
IS source current Tsp = 25 °C - -1.9 A I ≤ SM peak source current Tsp = 25 °C; tp 10 μs; pulsed - -7.5 A PMN50XP_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 October 2007 2 of 11
Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents
NXP Semiconductors PMN50XP P-channel TrenchMOS extremely low level FET 2. Pinning information Table 2. Pinning Pin Symbol Description Simplified outline Graphic Symbol
1 D drain 6 5 4 D 2 D drain 3 G gate 4 S source 1 2 3 G 5 D drain S 6 D drain 003aaa671
3. Ordering information Table 3. Ordering information Type number Package Name Description Version
PMN50XP TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457
4. Limiting values Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V ≥ ≤ DS drain-source voltage Tj 25 °C; Tj 150 °C - -20 V V ≥ ≤ DGR drain-gate voltage Tj 25 °C; Tj 150 °C; RGS = 20 kΩ - -20 V VGS gate-source voltage -12 12 V ID drain current Tsp = 25 °C; VGS = -4.5 V; see Figure 1 and 3 - -4.8 A Tsp = 100 °C; VGS = -4.5 V - -3 A IDM peak drain current Tsp = 25 °C; tp < 10 μs; pulsed; see Figure 3 - -19.4 A Ptot total power dissipation Tsp = 25 °C; see Figure 2 - 2.2 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C
Source-drain diode
IS source current Tsp = 25 °C - -1.9 A I ≤ SM peak source current Tsp = 25 °C; tp 10 μs; pulsed - -7.5 A PMN50XP_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 October 2007 2 of 11
Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents
