Datasheet ESDCAN03-2BM3Y (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | Automotive dual-line TVS in DFN for CAN bus |
| Pages / Page | 15 / 4 — ESDCAN03-2BM3Y. Characteristics (curves). 1.1. Figure 2. Maximum peak … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
ESDCAN03-2BM3Y. Characteristics (curves). 1.1. Figure 2. Maximum peak current versus initial junction
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Text Version of Document
ESDCAN03-2BM3Y Characteristics (curves) 1.1 Characteristics (curves) Figure 2. Maximum peak current versus initial junction Figure 3. Maximum peak pulse current versus exponential temperature (8/20 µs exponential waveform) pulse duration
I PP(A) IPP(A) 4 10 8/20 µs Tj initial = 25 °C 3 2 1 1 T t j (°C) p (ms) 0 0.1 0 25 50 75 100 125 150 175 200 0.01 0.1 1
Figure 4. Peak pulse current versus clamping voltage Figure 5. Junction capacitance versus reverse applied (8/20 µs exponential waveform) voltage
I (A) PP C (pF) 10 10 8/20 µs f = 1 MHz V = 30 mV osc RMS T = 25 °C j 1 V (V) CL V ( V) R 0.1 1 20 25 30 35 40 0 5 10 15 20
Figure 6. Leakage current versus junction temperature Figure 7. TLP
IR (nA) I (A) 100 30 VR = 24 V 20 10 10 0 1 -10 -20 T V( V) j( °C) 0.1 -30 25 50 75 100 125 150 175 -50 -40 -30 -20 -10 0 10 20 30 40 50
DS13559
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Rev 2 page 4/15
Document Outline 1 Characteristics 1.1 Characteristics (curves) 2 Package information 2.1 QFN-3L 1.1 x 1.0 x 0.55 package information 2.2 Packing information 3 Recommendation on PCB assembly 3.1 Footprint 3.2 Stencil opening design 3.3 Wettable flank profile 3.4 Solder paste 3.5 Placement 3.6 PCB design preference 3.7 Reflow profile 4 Ordering information Revision history
I PP(A) IPP(A) 4 10 8/20 µs Tj initial = 25 °C 3 2 1 1 T t j (°C) p (ms) 0 0.1 0 25 50 75 100 125 150 175 200 0.01 0.1 1
Figure 4. Peak pulse current versus clamping voltage Figure 5. Junction capacitance versus reverse applied (8/20 µs exponential waveform) voltage
I (A) PP C (pF) 10 10 8/20 µs f = 1 MHz V = 30 mV osc RMS T = 25 °C j 1 V (V) CL V ( V) R 0.1 1 20 25 30 35 40 0 5 10 15 20
Figure 6. Leakage current versus junction temperature Figure 7. TLP
IR (nA) I (A) 100 30 VR = 24 V 20 10 10 0 1 -10 -20 T V( V) j( °C) 0.1 -30 25 50 75 100 125 150 175 -50 -40 -30 -20 -10 0 10 20 30 40 50
DS13559
-
Rev 2 page 4/15
Document Outline 1 Characteristics 1.1 Characteristics (curves) 2 Package information 2.1 QFN-3L 1.1 x 1.0 x 0.55 package information 2.2 Packing information 3 Recommendation on PCB assembly 3.1 Footprint 3.2 Stencil opening design 3.3 Wettable flank profile 3.4 Solder paste 3.5 Placement 3.6 PCB design preference 3.7 Reflow profile 4 Ordering information Revision history
