Datasheet RDA5807M (RDA Microelectronics) - 8
| Manufacturer | RDA Microelectronics |
| Description | Single-Chip Broadcast FM Radio Tuner |
| Pages / Page | 23 / 8 — Serial Interface. 5.1. I2C Interface Timing. Table 5-1. I2C Interface … |
| Revision | 1.0 |
| File Format / Size | PDF / 775 Kb |
| Document Language | English |
Serial Interface. 5.1. I2C Interface Timing. Table 5-1. I2C Interface Timing Characteristics. PARAMETER. SYMBOL. TEST CONDITION. MIN. TYP
Model Line for this Datasheet
Text Version of Document
RDA Microelectronics, Inc. RDA5807M FM Tuner V1.0
5 Serial Interface 5.1 I2C Interface Timing Table 5-1 I2C Interface Timing Characteristics
(VDD = 3 V, TA = 25 °C, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
SCLK Frequency fscl 0 - 400 KHz SCLK High Time thigh 0.6 - - s SCLK Low Time tlow 1.3 - - s Setup Time for START Condition tsu:sta 0.6 - - s Hold Time for START Condition thd:sta 0.6 - - s Setup Time for STOP Condition tsu:sto 0.6 - - s SDIO Input to SCLK↑ Setup tsu:dat 100 - - ns SDIO Input to SCLK↓ Hold thd:dat 0 - 900 ns STOP to START Time tbuf 1.3 - - s SDIO Output Fall Time tf:out 20+0.1Cb - 250 ns SDIO Input, SCLK Rise/Fall Time tr:in / tf:in 20+0.1Cb - 300 ns Input Spike Suppression tsp - - 50 ns SCLK, SDIO Capacitive Loading Cb - - 50 pF Digital Input Pin Capacitance 5 pF tsu:sta thd:sta tsu:dat thd:dat tsp tsu:sto tbuf SDIO SCLK 1-7 8 9 1-7 8 1-7 8 9 9 START address r/w ACK data high byte ACK data low byte ACK STOP START Figure 5-1. I2C Interface Write Timing Diagram tsu:sta thd:sta tsu:dat thd:dat tsp tsu:sto tbuf SDIO SCLK 1-7 8 9 1-7 8 1-7 8 9 9 START address r/w ACK data high byte ACK data low byte NACK STOP START Figure 5-2. I2C Interface Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 8 of 23
5 Serial Interface 5.1 I2C Interface Timing Table 5-1 I2C Interface Timing Characteristics
(VDD = 3 V, TA = 25 °C, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
SCLK Frequency fscl 0 - 400 KHz SCLK High Time thigh 0.6 - - s SCLK Low Time tlow 1.3 - - s Setup Time for START Condition tsu:sta 0.6 - - s Hold Time for START Condition thd:sta 0.6 - - s Setup Time for STOP Condition tsu:sto 0.6 - - s SDIO Input to SCLK↑ Setup tsu:dat 100 - - ns SDIO Input to SCLK↓ Hold thd:dat 0 - 900 ns STOP to START Time tbuf 1.3 - - s SDIO Output Fall Time tf:out 20+0.1Cb - 250 ns SDIO Input, SCLK Rise/Fall Time tr:in / tf:in 20+0.1Cb - 300 ns Input Spike Suppression tsp - - 50 ns SCLK, SDIO Capacitive Loading Cb - - 50 pF Digital Input Pin Capacitance 5 pF tsu:sta thd:sta tsu:dat thd:dat tsp tsu:sto tbuf SDIO SCLK 1-7 8 9 1-7 8 1-7 8 9 9 START address r/w ACK data high byte ACK data low byte ACK STOP START Figure 5-1. I2C Interface Write Timing Diagram tsu:sta thd:sta tsu:dat thd:dat tsp tsu:sto tbuf SDIO SCLK 1-7 8 9 1-7 8 1-7 8 9 9 START address r/w ACK data high byte ACK data low byte NACK STOP START Figure 5-2. I2C Interface Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 8 of 23
