Datasheet ADIN1100 (Analog Devices) - 9

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Preliminary Technical Data ADIN1100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NB EL0 PD_E F_S EL1 ACI NB L L/SW M F_S C C/ 4_E _CT ACI RX /TX TX_CT M /RX K/ TX2P N/ O R/ ER _CLK _E _DV _CL D_0/ TXD_1 TXD_0 TX TX_E TX_ VDDI RX RX RX RX 40 39 38 37 36 35 34 33 32 31 TXD_2 1 30 RXD_1/MS_SEL TXD_3/MEDIA_CNV 2 29 RXD_2/PHYAD_0 LED_0 3 28 RXD_3/PHYAD_1 LINK_ST/PHYAD_2 4 27 MDC RESET_N 5 ADIN1100 26 MDIO LED_1 6 TOP VIEW 25 INT_N CLK25_REF 7 (Not to Scale) 24 DVDD_1P1 XTAL_I/CLK_IN 8 23 DLDO_1P1 XTAL_O 9 22 AVDD_L NC 10 21 CEXT_4 11 12 13 14 15 16 17 18 19 20 P NC N TXN RX TXP DD_H DD_H XT_1 XT_2 XT_3 RX AV AV CE CE CE NOTES 1. EXPOSED PAD. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE SOLDERED TO A METAL PLATE ON THE PCB FOR MECHANICAL REASONS AND TO GND.
Figure 4.
Table 7. Pin Function Descriptions (hardware pin configuration groupings are subject to change) Pin No. Mnemonic1 Description CLOCK INTERFACE
8 XTAL_I/CLK_IN Input for crystal/single ended 25 MHz reference clock or 50 MHz clock input for RMII. 9 XTAL_O Crystal output. If using a single ended reference clock on XTAL_I/CLK_IN, leave XTAL_O open circuit. See External Clock Input section. 7 CLK25_REF Analog reference clock output. The 25 MHz reference clock from the crystal oscillator is available on the CLK25_REF pin. This can be used as an input to another PHY.
MANAGEMENT INTERFACE
26 MDIO Management Data Input/Output synchronous to the MDC clock. This pin is open-drain and requires a 1.5 kΩ pull-up resistor to VDDIO. 27 MDC Management Data Clock input up to 2.5 MHz. 25 INT_N Management interface interrupt pin output. Open drain, active low output. A low on INT_N indicates an unmasked management interrupt. This pin requires a 1.5 kΩ pull-up resistor to VDDIO.
RESET
5 RESET_N Active low input. Hold low for >10 μs. See Hardware reset section. RESET_N does not require a pull-up resistor as there is an internal pull-up already in place. Rev. PrG | Page 9 of 70 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Characteristics Power-Up Timing Management Interface Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Theory of Operation Power Supply Domains MAC Interface MII Interface Mode RMII Interface Mode RGMII Interface Mode Auto-Negotiation Transmit Amplitude Resolution Master/Slave Resolution Management Interface Interrupt (INT_N) MDI Interface Reset Operation Power-On Reset Hardware Reset Software Reset PHY Subsystem Reset MAC Interface Reset Status LEDs LED Function Link Status Pin Powerdown Modes Hardware Powerdown Mode Software Powerdown Mode Hardware Configuration Pins Hardware Configuration Pin Functions PHY Address Configuration Software Powerdown after Reset Master/Slave Preference Transmit Amplitude MAC Interface Selection Media Convertor Bringing Up 10BASE-T1L Links Unmanaged PHY Operation Managed PHY Operation Power-up and Reset Complete Configuring the Part for Linking Advertisement of Transmit Level Operating Mode Advertisement of Master/Slave Successful Completion of Auto-Negotiation Link Status On-Chip Diagnostics Loopback Modes PMA Loopback PCS Loopback MAC Interface Loopback MAC Interface Remote Loopback External MII/RMII Loopback Frame Generator and Checker Frame Generator and Checker used with Remote Loopback with Two PHYs Test Modes Accessing the test modes Applications Information System Level Power Management Transmit Level = 1.0 V pk-pk Transmit Level = 2.4 V pk-pk Component Recommendations Crystal External Clock Input Register Summary Clause 22 Clause 45 Recommended Register Operation Latch Low Registers IEEE Duplicated Registers Read Modify Write Operation Clause 22 Register Details MII Control Register MII Status Register PHY Identifier 1 Register PHY Identifier 2 Register MMD Access Control Register MMD Access Register Clause 45 Register Details PMA/PMD Control 1 Register PMA/PMD Status 1 Register PMA/PMD MMD Devices in Package 1 Register PMA/PMD MMD Devices in Package 2 Register PMA/PMD Control 2 Register PMA/PMD Status 2 Register PMA/PMD Transmit Disable Register PMA/PMD Extended Abilities Register BASE-T1 PMA/PMD Extended Ability Register BASE-T1 PMA/PMD Control Register 10BASE-T1L PMA Control Register 10BASE-T1L PMA Status Register 10BASE-T1L Test Mode Control Register Frequency Offset Saturation Threshold for CR Stability Check Register Slave IIR Filter Change Echo Acquisition Clock Recovery Proportional Gain Register 10BASE-T1L PMA Link Status Register MSE Value Register PCS Control 1 Register PCS Status 1 Register PCS MMD Devices in Package 1 Register PCS MMD Devices in Package 2 Register PCS Status 2 Register 10BASE-T1L PCS Control Register 10BASE-T1L PCS Status Register AUTO-_NEGOTIATION MMD Devices in Package 1 Register AUTO-_NEGOTIATION MMD Devices in Package 2 Register BASE-T1 Autonegotiation Control Register BASE-T1 Autonegotiation Status Register BASE-T1 Autonegotiation Advertisement [15:0] Register BASE-T1 Autonegotiation Advertisement [31:16] Register BASE-T1 Autonegotiation Advertisement [47:32] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [47:32] Register BASE-T1 Autonegotiation Next Page Transmit [15:0] Register BASE-T1 Autonegotiation Next Page Transmit [31:16] Register BASE-T1 Autonegotiation Next Page Transmit [47:32] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [47:32] Register 10BASE-T1 Autonegotiation Control Register 10BASE-T1 Autonegotiation Status Register Extra Autonegotiation Status Register PHY Instantaneous Status Register Vendor Specific MMD 1 Device Identifier High Register Vendor Specific MMD 1 Device Identifier Low Register Vendor Specific 1 MMD Devices in Package Register Vendor Specific 1 MMD Devices in Package Register Vendor Specific MMD 1 Status Register System Interrupt Status Register System Interrupt Mask Register Software Reset Register Software Power-down Control Register PHY Subsystem Reset Register PHY MAC Interface Reset Register System Status Register CRSM Power Management Control Register MAC Interface Configuration Register CRSM Diagnostics Clock Control Register Package Configuration Values Register MDIO Control Register Pinmux Configuration 1 Register Pinmux Configuration 2 Register LED 0 ON/_OFF Blink Time Register LED 1 ON/_OFF Blink Time Register LED Control Register LED Polarity Register Vendor Specific MMD 2 Device Identifier High Register Vendor Specific MMD 2 Device Identifier Low Register Vendor Specific 2 MMD Devices in Package Register Vendor Specific 2 MMD Devices in Package Register Vendor Specific MMD 2 Status Register PHY Subsystem Interrupt Status Register PHY Subsystem Interrupt Mask Register Frame Checker Enable Register Frame Checker Interrupt Enable Register Frame Checker Transmit Select Register Receive Error Count Register Frame Checker Count High Register Frame Checker Count Low Register Frame Checker Length Error Count Register Frame Checker Alignment Error Count Register Frame Checker Symbol Error Count Register Frame Checker Oversized Frame Count Register Frame Checker Undersized Frame Count Register Frame Checker Odd Nibble Frame Count Register Frame Checker Odd Preamble Packet Count Register Frame Checker False Carrier Count Register Frame Generator Enable Register Frame Generator CONTROL/_RESTART Register Frame Generator Continuous Mode Enable Register Frame Generator Interrupt Enable Register Frame Generator Frame Length Register Frame Generator Number of Frames High Register Frame Generator Number of Frames Low Register Frame Generator Done Register RMII Configuration Register MAC Interface Loopbacks Configuration Register MAC Start Of Packet (SOP) Generation Control Register PCB Layout Recommendations PHY Package Layout Component Placement Crystal Placement and Routing Outline Dimensions