Datasheet PMG1-S0 (Infineon) - 5
| Manufacturer | Infineon |
| Description | Power Delivery Microcontroller Gen1 |
| Pages / Page | 34 / 5 — PMG1-S0 Datasheet. PMG1-S0 General Description. Features. Clocks and … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
PMG1-S0 Datasheet. PMG1-S0 General Description. Features. Clocks and Oscillators. Type-C Support and USB-PD Support. Power
Model Line for this Datasheet
Text Version of Document
PMG1-S0 Datasheet PMG1-S0 General Description
PMG1-S0 includes 64-KB flash, a complete Type-C USB-PD transceiver, a pull-down termination resistor RD to support Sink on the Type-C port, and system-level ESD protection. It is available in a 24-pin QFN package.
Features Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock
Type-C Support and USB-PD Support
■ Supports USB PD3.0 Version 2.0 Spec
Power
■ Termination resistor RD ■ VDDD (2.7 V–5.5 V) ■ Supports one USB Type-C port ■ VBUS (4.0 V–21.5 V)
Legacy/Proprietary Charging Block System-Level ESD Protection
■ Supports Apple charging 2.4A, BC 1.2 ■ On CC, VBUS_MON, USBDP, USBDM, P2.2, and P2.3 pins ■ Integrates all required terminations on USBDP/DM lines ■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C
System-Level Fault Protection Packages
■ VBUS to CC Short Protection ■ 24-pin QFN ■ On-chip overvoltage protection (OVP) and undervoltage ■ Supports extended industrial temperature range protection (UVP) (–40 °C to +105 °C)
32-bit MCU Subsystem
■ Arm Cortex-M0 CPU ■ 64-KB Flash ■ 8-KB SRAM Document Number: 002-31596 Rev. *B Page 4 of 33 Document Outline PMG1-S0 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S0 General Description Features Type-C Support and USB-PD Support Legacy/Proprietary Charging Block System-Level Fault Protection 32-bit MCU Subsystem Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview MCU Subsystem CPU Flash SROM USB-PD Subsystem (SS) USB-PD Physical Layer ADC Charger Detection VBUS Undervoltage and Overvoltage Protection VBUS Short Protection PFET Gate Drivers on VBUS Path VBUS Discharge FETs Integrated Digital Blocks Serial Communication Blocks (SCB) Timer/Counter/PWM Block (TCPWM) I/O Subsystem Power Systems Overview Pinouts Application Diagram Electrical Specifications Absolute Maximum Ratings Device-Level Specifications I/O Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-Speed Oscillator Power Down Gate Driver Specifications Analog to Digital Converter Memory Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
PMG1-S0 includes 64-KB flash, a complete Type-C USB-PD transceiver, a pull-down termination resistor RD to support Sink on the Type-C port, and system-level ESD protection. It is available in a 24-pin QFN package.
Features Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock
Type-C Support and USB-PD Support
■ Supports USB PD3.0 Version 2.0 Spec
Power
■ Termination resistor RD ■ VDDD (2.7 V–5.5 V) ■ Supports one USB Type-C port ■ VBUS (4.0 V–21.5 V)
Legacy/Proprietary Charging Block System-Level ESD Protection
■ Supports Apple charging 2.4A, BC 1.2 ■ On CC, VBUS_MON, USBDP, USBDM, P2.2, and P2.3 pins ■ Integrates all required terminations on USBDP/DM lines ■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C
System-Level Fault Protection Packages
■ VBUS to CC Short Protection ■ 24-pin QFN ■ On-chip overvoltage protection (OVP) and undervoltage ■ Supports extended industrial temperature range protection (UVP) (–40 °C to +105 °C)
32-bit MCU Subsystem
■ Arm Cortex-M0 CPU ■ 64-KB Flash ■ 8-KB SRAM Document Number: 002-31596 Rev. *B Page 4 of 33 Document Outline PMG1-S0 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S0 General Description Features Type-C Support and USB-PD Support Legacy/Proprietary Charging Block System-Level Fault Protection 32-bit MCU Subsystem Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview MCU Subsystem CPU Flash SROM USB-PD Subsystem (SS) USB-PD Physical Layer ADC Charger Detection VBUS Undervoltage and Overvoltage Protection VBUS Short Protection PFET Gate Drivers on VBUS Path VBUS Discharge FETs Integrated Digital Blocks Serial Communication Blocks (SCB) Timer/Counter/PWM Block (TCPWM) I/O Subsystem Power Systems Overview Pinouts Application Diagram Electrical Specifications Absolute Maximum Ratings Device-Level Specifications I/O Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-Speed Oscillator Power Down Gate Driver Specifications Analog to Digital Converter Memory Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
