Datasheet PMG1-S0 (Infineon) - 10

PMG1-S0 Datasheet
Functional Overview Charger Detection MCU Subsystem The charger detection block connected to the USBDP/DM pins
allow PMG1-S0 to detect conventional battery chargers
conforming to BC 1.2, and Apple Charging standard. CPU
The Cortex-M0 CPU in PMG1-S0 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating.
The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
PMG1-S0 has four break-point (address) comparators and two
watchpoint (data) comparators. VBUS Undervoltage and Overvoltage Protection
The PMG1-S0 chip has an integrated hardware block for VBUS
OVP/UVP with configurable thresholds and response times on
the Type C port.
VBUS Short Protection The USB-PD subsystem provides the interface to the Type-C
USB port. This subsystem comprises a high-voltage regulator,
OVP, and supply switch blocks. This subsystem also includes all
ESD required and supported on the Type-C port. PMG1-S0 provides four VBUS short protection pins: CC1, CC2,
P2.2, and P2.3. These pins are protected from accidental shorts
to high-voltage VBUS. Accidental shorts may occur because the
CC1 and CC2 pins are placed next to the VBUS pins in the USB
Type-C connector. A Power Delivery controller without the
high-voltage VBUS short protection will be damaged in the event
of accidental shorts. When the protection circuit is triggered,
PMG1-S0 can handle up to 17 V forever and between 17 V to
22 VDC for 1000 hours on the OVT pins. When a VBUS short
event occurs on the CC pins, a temporary high-ringing voltage is
observed due to the RLC elements in the USB Type-C cable.
Without PMG1-S0 connected, this ringing voltage can be twice
(44 V) the maximum VBUS voltage (21.5 V). However, when
PMG1-S0 is connected, it is capable of clamping temporary
high-ringing voltage and protecting the CC pin using IEC ESD
protection diodes. USB-PD Physical Layer PFET Gate Drivers on VBUS Path The USB-PD Physical Layer consists of a transmitter and
receiver that communicate BMC-encoded data over the CC
channel based on the PD 3.0 standard. All communication is
half-duplex. The Physical Layer or PHY practices collision
avoidance to minimize communication errors on the channel. PMG1-S0 has two integrated PFET gate drivers to drive external
PFETs on the VBUS consumer paths. The VBUS_FET_CTRL_0
gate driver has an active pull-up, and thus can drive high, low or
High-Z. Flash
The PMG1-S0 device has a flash module with one bank of 64-KB
flash, a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block.
SROM
A supervisory ROM that contains boot and configuration routines
is provided. USB-PD Subsystem (SS) The USB-PD block includes the RD termination resistor and
switch as required by the USB Type-C spec. The termination
resistor is required to implement connection detection, plug
orientation detection, and for establishing the sink power role. A
dead-battery RD termination enables identification as a sink
while the PMG1-S0 device is not powered.
ADC The VBUS_FET_CTRL_1 gate driver can drive only low or
high-Z, thus requiring an external pull-up. These pins are VBUS
voltage-tolerant.
VBUS Discharge FETs
PMG1-S0 also has two integrated VBUS discharge FETs used
to discharge VBUS to meet the USB-PD specification timing on
a detach condition. The ADC is a low-footprint 8-bit 125 ksps SAR ADC that is
available for general-purpose A-D conversion applications in the
chip. This ADC can be accessed from all GPIOs and the
USBDP/DM pins through an on-chip analog mux. PMG1-S0
contains two instances of the ADC. The voltage reference for the
ADCs is generated either from the VDDD supply or from internal
bandgap. When sensing the GPIO pin voltage with an ADC, the
pin voltage cannot exceed the VDDIO supply value. Document Number: 002-31596 Rev. *B Page 9 of 33