Datasheet PMG1-S2 (Infineon) - 4
| Manufacturer | Infineon |
| Description | Power Delivery Microcontroller Gen1 |
| Pages / Page | 34 / 4 — PMG1-S2 Datasheet. PMG1-S2 General Description. Features. Clocks and … |
| File Format / Size | PDF / 583 Kb |
| Document Language | English |
PMG1-S2 Datasheet. PMG1-S2 General Description. Features. Clocks and Oscillators. Type-C and USB-PD Support. Power
Model Line for this Datasheet
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PMG1-S2 Datasheet PMG1-S2 General Description
PMG1-S2 has 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20V-tolerant regulator, and a pair of FETs to switch a 5V (VCONN) supply. PMG1-S2 also integrates two pairs of gate drivers to control external VBUS FETs and system level ESD protection. PMG1-S2 is available in 40-QFN package.
Features Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock
Type-C and USB-PD Support
■ Supports one USB Type-C port
Power
■ Integrated USB Power Delivery 3.0 support ■ VSYS(2.7 V–5.5 V) ■ Integrated USB-PD BMC transceiver ■ VBUS (4.0 V–21.5 V) ■ Integrated VCONN FETs ■ 2x Integrated dual-output gate drivers for external VBUS FET ■ Configurable resistors RP and RD switch control ■ Dead Battery Detection support ■ Independent supply voltage pin for GPIO that allows 1.71 V to ■ Integrated fast role swap and extended data messaging 5.5 V signaling on the I/Os ■ Integrated Hardware based overcurrent protection (OCP) and overvoltage protection (OVP) ■ Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
32-bit MCU Subsystem System-Level ESD Protection
■ 48-MHz ARM Cortex-M0 CPU ■ On CC, SBU, USBDP, USBDM, and VBUS pins ■ 128-KB Flash ■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C ■ 8-KB SRAM
Packages Integrated Digital Blocks
■ Hardware Crypto block enables Authentication ■ 40-pin QFN ■ Full-Speed USB Device Controller supporting Billboard Device ■ Supports industrial temperature range (–40 °C to +105 °C) Class ■ Integrated timers and counters to meet response times required by the USB-PD protocol ■ Four run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality Document Number: 002-31598 Rev. *B Page 3 of 33 Document Outline PMG1-S2 Datasheet Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S2 General Description Features Type-C and USB-PD Support 32-bit MCU Subsystem Integrated Digital Blocks Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and the PMG1 SDK Functional Overview CPU and Memory Subsystem Crypto Block Integrated Billboard Device USB-PD Subsystem (USBPD SS) Full-Speed USB Subsystem Peripherals GPIO Power Systems Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications Digital Peripherals System Resources Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
PMG1-S2 has 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20V-tolerant regulator, and a pair of FETs to switch a 5V (VCONN) supply. PMG1-S2 also integrates two pairs of gate drivers to control external VBUS FETs and system level ESD protection. PMG1-S2 is available in 40-QFN package.
Features Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock
Type-C and USB-PD Support
■ Supports one USB Type-C port
Power
■ Integrated USB Power Delivery 3.0 support ■ VSYS(2.7 V–5.5 V) ■ Integrated USB-PD BMC transceiver ■ VBUS (4.0 V–21.5 V) ■ Integrated VCONN FETs ■ 2x Integrated dual-output gate drivers for external VBUS FET ■ Configurable resistors RP and RD switch control ■ Dead Battery Detection support ■ Independent supply voltage pin for GPIO that allows 1.71 V to ■ Integrated fast role swap and extended data messaging 5.5 V signaling on the I/Os ■ Integrated Hardware based overcurrent protection (OCP) and overvoltage protection (OVP) ■ Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
32-bit MCU Subsystem System-Level ESD Protection
■ 48-MHz ARM Cortex-M0 CPU ■ On CC, SBU, USBDP, USBDM, and VBUS pins ■ 128-KB Flash ■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C ■ 8-KB SRAM
Packages Integrated Digital Blocks
■ Hardware Crypto block enables Authentication ■ 40-pin QFN ■ Full-Speed USB Device Controller supporting Billboard Device ■ Supports industrial temperature range (–40 °C to +105 °C) Class ■ Integrated timers and counters to meet response times required by the USB-PD protocol ■ Four run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality Document Number: 002-31598 Rev. *B Page 3 of 33 Document Outline PMG1-S2 Datasheet Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S2 General Description Features Type-C and USB-PD Support 32-bit MCU Subsystem Integrated Digital Blocks Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and the PMG1 SDK Functional Overview CPU and Memory Subsystem Crypto Block Integrated Billboard Device USB-PD Subsystem (USBPD SS) Full-Speed USB Subsystem Peripherals GPIO Power Systems Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications Digital Peripherals System Resources Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
