Datasheet PMG1-S2 (Infineon) - 5

PMG1-S2 Datasheet Block Diagram Color Key:Power Modes PMG1-S2 MCU CYPM1211-40LQXI
Active/Sleep Deep Sleep
System Resources Power Clocks
(PCLK) trix Sleep Control ILO IMO ge ock Ma cl POR REF Clock Control I/O acka P eral le PWRSYS WDT riph -QFN WIC
Authentication
Pe mmab
Test
ra 40
Reset
Test Mode Entry Prog OVT), 2 Reset Control Digital DFT g
USB PD Subsystem
din XRES Analog DFT nclu Os (i O) m GPI e
CPU Subsystem
(MMI 20 ct syst nne VBUS Under Voltage/ ub SWD/TC Over Voltage erco S IO Cortex M0 Int 48 MHz ) eral B riph FAST MUL r AH Pe NVIC, IRQMUX Laye e SPCIF ngl Flash (Si 128 KB ect nn Read Accelerator s, IEC ESD erco Pad Int SRAM m 8 KB Syste SRAM Controller FS PHY ROM 8 KB ROM Controller Document Number: 002-31598 Rev. *B Page 4 of 33 Document Outline PMG1-S2 Datasheet Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S2 General Description Features Type-C and USB-PD Support 32-bit MCU Subsystem Integrated Digital Blocks Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and the PMG1 SDK Functional Overview CPU and Memory Subsystem Crypto Block Integrated Billboard Device USB-PD Subsystem (USBPD SS) Full-Speed USB Subsystem Peripherals GPIO Power Systems Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications Digital Peripherals System Resources Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support