Datasheet PMG1-S2 (Infineon) - 31

PMG1-S2 Datasheet Acronyms Table 45. Acronyms Used in this Document
(continued)
Table 45. Acronyms Used in this Document Acronym Description
OVP overvoltage protection
Acronym Description
OVT over voltage tolerant ADC analog-to-digital converter PCB printed circuit board AES advanced encryption standard PD power delivery AHB AMBA (advanced microcontroller bus architecture) high-performance bus PGA programmable gain amplifier API application programming interface PHY physical layer Arm® advanced RISC machine, a CPU architecture POR power-on reset BMC Biphase Mark Code PRES precise power-on reset CC configuration channel PRNG pseudo random number generation CPU central processing unit PWM pulse-width modulator RAM random-access memory CRC cyclic redundancy check, an error-checking protocol RCP reverse current protection, supported in CS current sense Source Configuration only DFP downstream facing port RISC reduced-instruction-set computing digital input/output, GPIO with only digital RMS root-mean-square DIO capabilities, no analog. See GPIO. RTC real-time clock DRP dual role port RX receive electrically erasable programmable read-only SAR successive approximation register EEPROM memory SCB serial communication block electronically marked cable assembly, a USB SCL I2C serial clock cable that includes an IC that reports cable EMCA characteristics (e.g., current rating) to the SCP short circuit protection, supported in Source Configuration only Type-C ports EMI electromagnetic interference SDA I2C serial data ESD electrostatic discharge S/H sample and hold SHA secure hash algorithm FS full-speed GPIO general-purpose input/output SPI Serial Peripheral Interface, a communications protocol HPD hot plug detect SRAM static random access memory IC integrated circuit SWD serial wire debug, a test protocol IDE integrated development environment TCPWM timer/counter pulse-width modulator I2C, or IIC Inter-Integrated Circuit, a communications TRNG true random number generation protocol ILO internal low-speed oscillator, see also IMO TX transmit IMO internal main oscillator, see also ILO a new standard with a slimmer USB connector Type-C and a reversible cable, capable of sourcing up IOSS input/output subsystem to 100 W of power I/O input/output, see also GPIO UART Universal Asynchronous Transmitter Receiver, LDO low-dropout regulator a communications protocol LVD low-voltage detect USB Universal Serial Bus LVTTL low-voltage transistor-transistor logic USB PD USB Power Delivery MCU microcontroller unit USB-FS USB Full-Speed MMIO memory mapped input/output USBIO USB input/output, PMG1-S2 pins used to NC no connect connect to a USB port NMI nonmaskable interrupt USBPD SS USB PD subsystem NVIC nested vectored interrupt controller UVP under voltage protection opamp operational amplifier VDM vendor defined messages OCP overcurrent protection XRES external reset I/O pin Document Number: 002-31598 Rev. *B Page 30 of 33 Document Outline PMG1-S2 Datasheet Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S2 General Description Features Type-C and USB-PD Support 32-bit MCU Subsystem Integrated Digital Blocks Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and the PMG1 SDK Functional Overview CPU and Memory Subsystem Crypto Block Integrated Billboard Device USB-PD Subsystem (USBPD SS) Full-Speed USB Subsystem Peripherals GPIO Power Systems Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications Digital Peripherals System Resources Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support