Datasheet ADSP-TS101S (Analog Devices) - 6

ADSP-TS101S GLOBAL SPACE 0xFFFFFFFF HOST (MSH) INTERNAL SPACE 0x10000000 0x003FFFFF BANK 1 E (MS1) C A P S 0x0C000000 Y 0x00300000 R O M BANK 0 E (MS0) M L A RESERVED N 0x08000000 0x00280000 R E T X SDRAM E (MSSD) 0x00200000 0x04000000 PROCESSOR I D 7 E C 0x03C00000 A PROCESSOR I D 6 P S 0x03800000 Y PROCESSOR I D 5 R 0x001807FF O 0x03400000 I NTE RNAL REG ISTERS (UREGS ) M PROCESSOR I D 4 E 0x00180000 0x03000000 M EACH IS A COPY R PROCESSOR I D 3 OF INTERNAL SPACE RESERVED O 0x02C00000 S S PROCESSOR I D 2 E 0x0010FFFF 0x02800000 C INTERNAL MEMORY 2 O PROCESSOR I D 1 R 0x00100000 0x02400000 IP T PROCESSOR I D 0 L RESERVED U 0x02000000 M BROADCAST 0x0008FFFF 0x01C00000 INTERNAL MEMORY 1 0x00080000 RESERV ED RESERVED 0x0000FFFF 0x003FFFFF INTERNAL MEMORY 0 INTERNAL MEMORY 0x00000000 0x00000000
Figure 3. Memory Map
EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS101S processor’s external port provides the pro- The external port supports pipelined, slow, and SDRAM proto- cessor’s interface to off-chip memory and peripherals. The cols. Addressing of external memory devices and memory- 4G word address space is included in the DSP’s unified address mapped peripherals is facilitated by on-chip decoding of high- space. The separate on-chip buses—three 128-bit data buses and order address lines to generate memory bank select signals. three 32-bit address buses—are multiplexed at the external port The ADSP-TS101S provides programmable memory, pipeline to create an external system bus with a single 64-bit data bus depth, and idle cycle for synchronous accesses, and external and a single 32-bit address bus. The external port supports data acknowledge controls to support interfacing to pipelined or transfer rates of 800M bytes per second over external bus. slow devices, host processors, and other memory-mapped The external bus can be configured for 32- or 64-bit operation. peripherals with variable access, hold, and disable time When the system bus is configured for 64-bit operation, the requirements. lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits connect to odd addresses. Rev. D | Page 6 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide