Datasheet RAA227063 (Renesas) - 4

Nov 29, 20 R16
RAA2 1. Overview
D S0
270
045
1.1 Typical Application Circuits
21
63
EU0
Dat VIN = 4.5V to 60V
1 0
a
1
shee
Rev
E t G
.
D 2 V D
1.01
N 1 R L H RI FB VM PG SW SW VD CP CP VB VCP osc 500mA Buck-boost MCU 1/2 w/ VIN UVLO, VOUT OV/ Charge Pump w/ COMP GHA UV, OCP VCP UVLO HS Level SHA AUXVCC Shifter VDD MCU FBLDO LDO2 LDO3 GLA LS GND VCC LDO1 SPA SGND
l
GHB HS
l
EN
a
GPIO Level SHB HIA Shifter
H
LIA Core Logic GLB Smart Gate Drive HIB LS Protection DPWM (or LIB GPIO) HIC Control Inputs SPB & LIC Configuration Interface IDRV/SDI GHC MODE/SDO HS Level CSGAIN/SCLK SHC VBRIDGE Shifter VDSTH/nSCS SHA SPA GLC DT/IFSEL/BEN VDS Shoot- LS SHB through/OCP Protection SPB AUXVCC SHC SPC SPC SPA Fault Output nFault GPIO SNA CSOA SPB A/D

Amplifier stages support flexible configuration to: CSOB/SNS_SEL2 A/D 1) Up to 3-phase current sensing (Shunt or r SNB/BEPHSEL2 DS(ON)) 2) Up to 2-phase current sensing + BEMF sensing CSOC/BEMFO/SNS_SEL1

Internal S/H of sensed signal can be enabled for shunt sense and SPC A/D BEMF sense VREF

See the Current Sensing and BEMF Sensing section SNC/BEPHSEL1 VREF VBRIDGE VCC SHA POR VBRIDGEUVLO SHB COMMON SHC
Page
EPAD
4
Figure 2. RAA227063 Simplified Diagram and Application – Hardware Interface Operation, BEMF Sensing Disabled, No S/H for Current Sense
Document Outline Applications Features Contents 1. Overview 1.1 Typical Application Circuits 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Thermal Information 3.3 Recommended Operating Conditions 3.4 Electrical Specifications 4. Typical Performance Curves 5. Functional Description 5.1 Modes of Operation and Power-On Sequence 5.1.1 Definitions of State of Different Modes 5.1.2 Mode Transition 5.1.3 Modes of Operation 5.1.3.1 Gate Driver Control Modes 5.1.3.2 3-phase HI/LI Mode 5.1.3.3 3-phase PWM Mode 5.1.4 Gate Driver Structure and Feature 5.1.4.1 Driver Structure 5.1.4.2 Adjustable Slew-Rate 5.1.4.3 Driver Robustness Enhancement 5.1.4.4 Gate Drive Diagram 5.1.4.5 Gate Drive Scheme in 3-phase HI/LI Mode 5.1.5 Power Architecture 5.1.5.1 Power Architecture Overview 5.1.5.2 Low-Side Driver Supply (VDRV) 5.1.5.3 Charge Pump 5.1.5.4 VCC Supply 5.1.5.5 MCU AUXVCC Supply 5.1.6 Power-On Sequence 5.2 Fault Management 5.2.1 Fault Conditions Types 5.2.2 nFAULT Indicator 5.3 Current Sensing and BEMF Sensing 5.3.1 Overview 5.3.2 Details on Different Sensing Configurations 5.3.2.1 Configuration 1 5.3.2.2 Configuration 2 5.3.2.3 Configuration 3 5.3.2.4 Configuration 4 5.3.2.5 Configuration 5 5.3.2.6 Configuration 6 5.3.2.7 Configuration 7 5.3.2.8 Configuration 8 5.3.2.9 Configuration 9 5.3.3 Structure of Amplifiers CSA, CSB, and CSC 5.3.4 BEMF Sensing Control Signal Logic 5.3.5 Multiplexer Control Signal Logic 5.3.6 Sample and Hold Timing Logic 5.3.7 Low-Side rDS(ON) Current Sensing Timing Logic 5.4 Hardware Interface for Parameter Setting 5.4.1 Parameter Setting Tables 5.5 Serial Peripheral Interface (SPI) 5.5.1 Communication Protocol 5.5.2 Timing Diagram 6. Register Map 7. Package Outline Drawing 8. Ordering Information 9. Revision History