Datasheet NXS0506 (Nexperia) - 7
| Manufacturer | Nexperia |
| Description | SD 3.0-compatible memory card integrated auto-direction control and level translator with EMI filter and ESD protection |
| Pages / Page | 17 / 7 — Nexperia. NXS0506. SD 3.0-compatible memory card integrated … |
| Revision | 31012022 |
| File Format / Size | PDF / 269 Kb |
| Document Language | English |
Nexperia. NXS0506. SD 3.0-compatible memory card integrated auto-direction control and level translator with EMI filter and
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Nexperia NXS0506 SD 3.0-compatible memory card integrated auto-direction control and level translator with EMI filter and ESD protection 12. Static characteristics Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); unless otherwise specified.
Symbol Parameter Conditions Tamb = -40 °C to 85 °C Unit Min Typ[1] Max Automatic enable feature: VCCB
Ven device enable VCCA ≥ 1.0 V; VCCB rising edge 0.9 1.2 1.5 V voltage level Vdis device disable VCCA ≥ 1.0 V; VCCB falling edge 0.65 1.0 1.3 V voltage level
Host-side input signals: CMDA, DAT0A to DAT3A and CLKA
VIH HIGH-level 1.1 V ≤ VCCA ≤ 1.95 V 0.65VCCA - VCCA + 0.3 V input voltage VIL LOW-level 1.1 V ≤ VCCA ≤ 1.95 V -0.3 - 0.35VCCA V input voltage II input leakage CLKA; VCCA = 1.8 V; VI = 0 V to 1.95 V - - 1 µA current
Host-side output signals: CMDA and DAT0A to DAT3A
VOH HIGH-level IO = -2 µA; VI = VIH (card side) 0.8VCCA - VCCA + 0.3 V output voltage 1.1 V ≤ VCCA ≤ 1.95 V VOL LOW-level IO = 2 mA; VI = VIL (card side) -0.3 - 0.15VCCA V output voltage 1.1 V ≤ VCCA ≤ 1.95 V
Host-side output signals: CLKFB
VOH HIGH-level IO = -2 mA; VI = VIH (host side) 0.8VCCA - VCCA + 0.3 V output voltage 1.1 V ≤ VCCA ≤ 1.95 V VOL LOW-level IO = 2 mA; VI = VIL (host side) -0.3 - 0.15VCCA V output voltage 1.1 V ≤ VCCA ≤ 1.95 V
Card-side input signals: CMDB and DAT0B to DAT3B
VIH HIGH-level 1.7 V ≤ VCCB ≤ 3.6 V 0.625VCCB - VCCB + 0.3 V input voltage VIL LOW-level 1.7 V ≤ VCCB ≤ 1.95 V -0.3 - 0.35VCCB V input voltage 2.7 V ≤ VCCB ≤ 3.6 V -0.3 - 0.30VCCB V
Card-side output signal: CMDB, DAT0B to DAT3B and CLKB
VOH HIGH-level CLKB; VCCB = 1.7 V; IO = -2 mA; 0.85VCCB - 2.0 V output voltage VI = VIH (host side) CLKB; VCCB = 2.7 V; IO = -4 mA; 0.85VCCB - VCCB + 0.3 V VI = VIH (host side) CMDB, DATnB; VCCB = 1.7 V; 0.85VCCB - 2.0 V IO = -2 µA; VI = VIH (host side) VOL Low-level IO = 2 mA; VI = VIL (host side); -0.3 - 0.125VCCB V output voltage VCCB = 1.7 V IO = 4 mA; VI = VIL (host side); -0.3 - 0.125VCCB V VCCB = 2.7 V NXS0506 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. Al rights reserved
Product data sheet Rev. 1 — 31 January 2022 7 / 17
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Marking 6. Block diagram 7. Functional diagram 8. Pinning information 8.1. Pinning 8.2. Pin description 9. Functional description 9.1. Level translator 9.2. Enable and direction control 9.3. Feedback clock channel 9.4. EMI filter 9.5. ESD protection 9.6. Pin and channel naming 10. Limiting values 11. Recommended operating conditions 12. Static characteristics 13. Dynamic characteristics 13.1. Level translator 14. Application information 14.1. PCB design guidelines 15. Design and assembly recommendations 15.1. PCB design guidelines 15.2. PCB assembly guidelines for Pb-free soldering 16. Package outline 17. Abbreviations 18. Revision history 19. Legal information Contents
Nexperia NXS0506 SD 3.0-compatible memory card integrated auto-direction control and level translator with EMI filter and ESD protection 12. Static characteristics Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); unless otherwise specified.
Symbol Parameter Conditions Tamb = -40 °C to 85 °C Unit Min Typ[1] Max Automatic enable feature: VCCB
Ven device enable VCCA ≥ 1.0 V; VCCB rising edge 0.9 1.2 1.5 V voltage level Vdis device disable VCCA ≥ 1.0 V; VCCB falling edge 0.65 1.0 1.3 V voltage level
Host-side input signals: CMDA, DAT0A to DAT3A and CLKA
VIH HIGH-level 1.1 V ≤ VCCA ≤ 1.95 V 0.65VCCA - VCCA + 0.3 V input voltage VIL LOW-level 1.1 V ≤ VCCA ≤ 1.95 V -0.3 - 0.35VCCA V input voltage II input leakage CLKA; VCCA = 1.8 V; VI = 0 V to 1.95 V - - 1 µA current
Host-side output signals: CMDA and DAT0A to DAT3A
VOH HIGH-level IO = -2 µA; VI = VIH (card side) 0.8VCCA - VCCA + 0.3 V output voltage 1.1 V ≤ VCCA ≤ 1.95 V VOL LOW-level IO = 2 mA; VI = VIL (card side) -0.3 - 0.15VCCA V output voltage 1.1 V ≤ VCCA ≤ 1.95 V
Host-side output signals: CLKFB
VOH HIGH-level IO = -2 mA; VI = VIH (host side) 0.8VCCA - VCCA + 0.3 V output voltage 1.1 V ≤ VCCA ≤ 1.95 V VOL LOW-level IO = 2 mA; VI = VIL (host side) -0.3 - 0.15VCCA V output voltage 1.1 V ≤ VCCA ≤ 1.95 V
Card-side input signals: CMDB and DAT0B to DAT3B
VIH HIGH-level 1.7 V ≤ VCCB ≤ 3.6 V 0.625VCCB - VCCB + 0.3 V input voltage VIL LOW-level 1.7 V ≤ VCCB ≤ 1.95 V -0.3 - 0.35VCCB V input voltage 2.7 V ≤ VCCB ≤ 3.6 V -0.3 - 0.30VCCB V
Card-side output signal: CMDB, DAT0B to DAT3B and CLKB
VOH HIGH-level CLKB; VCCB = 1.7 V; IO = -2 mA; 0.85VCCB - 2.0 V output voltage VI = VIH (host side) CLKB; VCCB = 2.7 V; IO = -4 mA; 0.85VCCB - VCCB + 0.3 V VI = VIH (host side) CMDB, DATnB; VCCB = 1.7 V; 0.85VCCB - 2.0 V IO = -2 µA; VI = VIH (host side) VOL Low-level IO = 2 mA; VI = VIL (host side); -0.3 - 0.125VCCB V output voltage VCCB = 1.7 V IO = 4 mA; VI = VIL (host side); -0.3 - 0.125VCCB V VCCB = 2.7 V NXS0506 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. Al rights reserved
Product data sheet Rev. 1 — 31 January 2022 7 / 17
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Marking 6. Block diagram 7. Functional diagram 8. Pinning information 8.1. Pinning 8.2. Pin description 9. Functional description 9.1. Level translator 9.2. Enable and direction control 9.3. Feedback clock channel 9.4. EMI filter 9.5. ESD protection 9.6. Pin and channel naming 10. Limiting values 11. Recommended operating conditions 12. Static characteristics 13. Dynamic characteristics 13.1. Level translator 14. Application information 14.1. PCB design guidelines 15. Design and assembly recommendations 15.1. PCB design guidelines 15.2. PCB assembly guidelines for Pb-free soldering 16. Package outline 17. Abbreviations 18. Revision history 19. Legal information Contents
