Datasheet ADGS1414D (Analog Devices)
| Manufacturer | Analog Devices |
| Description | SPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High Density Octal SPST Switch |
| Pages / Page | 28 / 1 — SPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High. Density Octal SPST Switch. Data … |
| File Format / Size | PDF / 558 Kb |
| Document Language | English |
SPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High. Density Octal SPST Switch. Data Sheet. ADGS1414D. FEATURES. FUNCTIONAL BLOCK DIAGRAM
Model Line for this Datasheet
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link to page 28
SPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High Density Octal SPST Switch Data Sheet ADGS1414D FEATURES FUNCTIONAL BLOCK DIAGRAM SPI with error detection VDD VSS Includes CRC, invalid read and write address, and SCLK count error detection ADGS1414D Supports burst mode and daisy-chain mode Industry-standard SPI Mode 0 and Mode 3 interface S1 D1 S2 D2 compatible S3 D3 Integrated passive components S4 D4 Route through of digital signals and supplies S5 D5 Guaranteed break-before-make switching allowing external S6 D6 wiring of switches to deliver multiplexer configurations S7 D7 1.5 Ω typical on resistance at 25°C (±15 V dual supply) S8 D8 VL 0.3 Ω typical on resistance flatness at 25°C (±15 V dual supply) SPI 0.1 Ω typical on resistance match between channels at 25°C SDO INTERFACE (±15 V dual supply) VSS to VDD analog signal range
001
Fully specified at ±15 V, ±5 V, and +12 V SCLK SDI CS RESET/VL 1.8 V logic compatibility with 2.7 V ≤ V
23895-
L ≤ 3.3 V (excludes SPI
Figure 1.
readback to a 1.8 V device) 4 mm × 5 mm, 30-terminal LGA
The ADGS1414D is suited to high density switching applications, such as large switching matrices and fanout
APPLICATIONS
applications.
Automated test equipment
Each switch conducts equal y well in both directions when on,
Data acquisition systems
and each switch has an input signal range that extends to the
Sample-and-hold systems
supplies. In the off condition, signal levels up to the supplies
Audio and video signal routing
are blocked.
Communications systems Relay replacement
Multifunction pin names may be referenced by their relevant function only.
GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The ADGS1414D contains eight independent SPST switches. A serial peripheral interface (SPI) controls the switches. The SPI 1. The SPI removes the need for parallel conversion and logic has robust error detection features, such as cyclic redundancy traces and reduces the general-purpose input and output check (CRC) error detection, invalid read and write address (GPIO) channel count. detection, and SCLK count error detection. 2. Daisy-chain mode removes additional logic traces when multiple devices are used. It is possible to daisy-chain multiple ADGS1414D devices 3. Route through of digital signals and supplies eases routing together. Daisy-chain mode enables the configuration of and allows for an increase in channel density. multiple devices with a minimal amount of digital lines. The 4. Integrated passive components eliminate the need for route of digital signals and supplies through the ADGS1414D external passive components. al ows for a further increase in channel density. Integrated 5. CRC error detection, invalid read and write address passive components eliminate the need for external passive detection, and SCLK count error detection ensure a robust components. digital interface. 6. CRC, invalid read and write address, and SCLK error detection capabilities al ow for the use of the ADGS1414D in safety critical systems. 7. Minimum distortion.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply ±5 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADGS1414D ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read and Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information System Channel Density Route Through Pins Integrated Passive Components Break-Before-Make Switching Digital Input Buffers Power Supply Rails Power Supply Recommendations 1.8 V Logic Compatibility Register Summary Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Software Reset Register Outline Dimensions Ordering Guide
SPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High Density Octal SPST Switch Data Sheet ADGS1414D FEATURES FUNCTIONAL BLOCK DIAGRAM SPI with error detection VDD VSS Includes CRC, invalid read and write address, and SCLK count error detection ADGS1414D Supports burst mode and daisy-chain mode Industry-standard SPI Mode 0 and Mode 3 interface S1 D1 S2 D2 compatible S3 D3 Integrated passive components S4 D4 Route through of digital signals and supplies S5 D5 Guaranteed break-before-make switching allowing external S6 D6 wiring of switches to deliver multiplexer configurations S7 D7 1.5 Ω typical on resistance at 25°C (±15 V dual supply) S8 D8 VL 0.3 Ω typical on resistance flatness at 25°C (±15 V dual supply) SPI 0.1 Ω typical on resistance match between channels at 25°C SDO INTERFACE (±15 V dual supply) VSS to VDD analog signal range
001
Fully specified at ±15 V, ±5 V, and +12 V SCLK SDI CS RESET/VL 1.8 V logic compatibility with 2.7 V ≤ V
23895-
L ≤ 3.3 V (excludes SPI
Figure 1.
readback to a 1.8 V device) 4 mm × 5 mm, 30-terminal LGA
The ADGS1414D is suited to high density switching applications, such as large switching matrices and fanout
APPLICATIONS
applications.
Automated test equipment
Each switch conducts equal y well in both directions when on,
Data acquisition systems
and each switch has an input signal range that extends to the
Sample-and-hold systems
supplies. In the off condition, signal levels up to the supplies
Audio and video signal routing
are blocked.
Communications systems Relay replacement
Multifunction pin names may be referenced by their relevant function only.
GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The ADGS1414D contains eight independent SPST switches. A serial peripheral interface (SPI) controls the switches. The SPI 1. The SPI removes the need for parallel conversion and logic has robust error detection features, such as cyclic redundancy traces and reduces the general-purpose input and output check (CRC) error detection, invalid read and write address (GPIO) channel count. detection, and SCLK count error detection. 2. Daisy-chain mode removes additional logic traces when multiple devices are used. It is possible to daisy-chain multiple ADGS1414D devices 3. Route through of digital signals and supplies eases routing together. Daisy-chain mode enables the configuration of and allows for an increase in channel density. multiple devices with a minimal amount of digital lines. The 4. Integrated passive components eliminate the need for route of digital signals and supplies through the ADGS1414D external passive components. al ows for a further increase in channel density. Integrated 5. CRC error detection, invalid read and write address passive components eliminate the need for external passive detection, and SCLK count error detection ensure a robust components. digital interface. 6. CRC, invalid read and write address, and SCLK error detection capabilities al ow for the use of the ADGS1414D in safety critical systems. 7. Minimum distortion.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply ±5 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADGS1414D ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read and Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information System Channel Density Route Through Pins Integrated Passive Components Break-Before-Make Switching Digital Input Buffers Power Supply Rails Power Supply Recommendations 1.8 V Logic Compatibility Register Summary Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Software Reset Register Outline Dimensions Ordering Guide
