Datasheet ADG5433, ADG5434 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | High Voltage Latch-Up Proof, Triple/Quad SPDT Switches |
| Pages / Page | 24 / 10 — ADG5433/ADG5434. Data Sheet. PIN CONFIGURATIONS AND FUNCTION … |
| Revision | C |
| File Format / Size | PDF / 428 Kb |
| Document Language | English |
ADG5433/ADG5434. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. GND. S1A. IN1. D1 1. 12 EN. ADG5433. S1B 2. 11 VSS. TOP VIEW. S1B
Model Line for this Datasheet
Text Version of Document
ADG5433/ADG5434 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A D D 1 D N 1 S V G NI 6 5 4 3 1 1 1 1 V 1 16 DD GND S1A 2 15 IN1 D1 1 12 EN ADG5433 D1 3 14 EN S1B 2 11 VSS TOP VIEW S1B 4 ADG5433 13 V S2B 3 10 S3B SS (Not to Scale) TOP VIEW D2 4 9 D3 S2B 5 12 S3B (Not to Scale) D2 6 11 D3 5 6 7 8 S2A 7 2 3 10 S3A A A 2 N N 3 S I I S
03
IN2 8 9 IN3
0 7-
NOTES
005 20
1. EXPOSED PAD IS TIED TO SUBSTRATE, V
09
SS.
9207- 0 Figure 3. ADG5433 TSSOP Pin Configuration Figure 4. ADG5433 LFCSP_WQ Pin Configuration
Table 8. ADG5433 Pin Function Descriptions Pin No. TSSOP LFCSP_WQ Mnemonic Description
1 15 VDD Most Positive Power Supply Potential. 2 16 S1A Source Terminal 1A. This pin can be an input or an output. 3 1 D1 Drain Terminal 1. This pin can be an input or an output. 4 2 S1B Source Terminal 1B. This pin can be an input or an output. 5 3 S2B Source Terminal 2B. This pin can be an input or an output. 6 4 D2 Drain Terminal 2. This pin can be an input or an output. 7 5 S2A Source Terminal 2A. This pin can be an input or an output. 8 6 IN2 Logic Control Input 2. 9 7 IN3 Logic Control Input 3. 10 8 S3A Source Terminal 3A. This pin can be an input or an output. 11 9 D3 Drain Terminal 3. This pin can be an input or an output. 12 10 S3B Source Terminal 3B. This pin can be an input or an output. 13 11 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 14 12 EN Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches. 15 13 IN1 Logic Control Input 1. 16 14 GND Ground (0 V) Reference. EP Exposed The exposed pad is connected internally. For increased reliability of the solder joints and maximum Pad thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG5433 Truth Table EN INx SxA SxB
1 X Off Off 0 0 Off On 0 1 On Off Rev. C | Page 10 of 24 Document Outline Features Applications Functional Block Diagrams General Description Product Highlights Revision History Specifications ±15 V Dual Supply ±20 V Dual Supply 12 V Single Supply 36 V Single Supply Continuous Current per Channel, Sx or Dx Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Trench Isolation Applications Information Outline Dimensions Ordering Guide
03
IN2 8 9 IN3
0 7-
NOTES
005 20
1. EXPOSED PAD IS TIED TO SUBSTRATE, V
09
SS.
9207- 0 Figure 3. ADG5433 TSSOP Pin Configuration Figure 4. ADG5433 LFCSP_WQ Pin Configuration
Table 8. ADG5433 Pin Function Descriptions Pin No. TSSOP LFCSP_WQ Mnemonic Description
1 15 VDD Most Positive Power Supply Potential. 2 16 S1A Source Terminal 1A. This pin can be an input or an output. 3 1 D1 Drain Terminal 1. This pin can be an input or an output. 4 2 S1B Source Terminal 1B. This pin can be an input or an output. 5 3 S2B Source Terminal 2B. This pin can be an input or an output. 6 4 D2 Drain Terminal 2. This pin can be an input or an output. 7 5 S2A Source Terminal 2A. This pin can be an input or an output. 8 6 IN2 Logic Control Input 2. 9 7 IN3 Logic Control Input 3. 10 8 S3A Source Terminal 3A. This pin can be an input or an output. 11 9 D3 Drain Terminal 3. This pin can be an input or an output. 12 10 S3B Source Terminal 3B. This pin can be an input or an output. 13 11 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 14 12 EN Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches. 15 13 IN1 Logic Control Input 1. 16 14 GND Ground (0 V) Reference. EP Exposed The exposed pad is connected internally. For increased reliability of the solder joints and maximum Pad thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG5433 Truth Table EN INx SxA SxB
1 X Off Off 0 0 Off On 0 1 On Off Rev. C | Page 10 of 24 Document Outline Features Applications Functional Block Diagrams General Description Product Highlights Revision History Specifications ±15 V Dual Supply ±20 V Dual Supply 12 V Single Supply 36 V Single Supply Continuous Current per Channel, Sx or Dx Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Trench Isolation Applications Information Outline Dimensions Ordering Guide
