Data SheetADG5404PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSENA0A1NC16151413VSS 112 GNDA0114 A1NC 211 VADG5404DDTOP VIEWEN3102S1S313 GND(Not so Scale)S2 49S4V3SS12 VADG5404DDS1411S3TOP VIEW5678(Not to Scale)S2510 S4DNCNCNCD69NCNOTES 03 NC78NC1. NC = NO CONNECT. 0 02 0 03- 2. EXPOSED PAD TIED TO SUBSTRATE, V 3- SS. 092 NC = NO CONNECT 20 09 Figure 2. TSSOP Pin Configuration Figure 3. LFCSP Pin Configuration Table 7. Pin Function DescriptionsPin No.TSSOP LFCSPMnemonic Description 1 15 A0 Logic Control Input. 2 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switches. 3 1 VSS Most Negative Power Supply Potential. 4 3 S1 Source Terminal. Can be an input or an output. 5 4 S2 Source Terminal. Can be an input or an output. 6 6 D Drain Terminal. Can be an input or an output. 7 to 9 2, 5, 7, 8, 13 NC No Connection. 10 9 S4 Source Terminal. Can be an input or an output. 11 10 S3 Source Terminal. Can be an input or an output. 12 11 VDD Most Positive Power Supply Potential. 13 12 GND Ground (0 V) Reference. 14 14 A1 Logic Control Input. EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. TRUTH TABLETable 8. ENA1A0S1S2S3S4 0 X1 X1 Off Off Off Off 1 0 0 On Off Off Off 1 0 1 Off On Off Off 1 1 0 Off Off On Off 1 1 1 Off Off Off On 1 X = don’t care. Rev. B | Page 9 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±20 V DUAL SUPPLY +12 V SINGLE SUPPLY +36 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, S OR D ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY TRENCH ISOLATION APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE