Datasheet ADG428, ADG429 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | LC2MOS Latchable 4-/8-Channel High Performance Analog Multiplexers |
| Pages / Page | 12 / 5 — ADG428/ADG429. TERMINOLOGY. ADG428 Truth Table. WR RS. ON SWITCH. ADG429 … |
| Revision | C |
| File Format / Size | PDF / 164 Kb |
| Document Language | English |
ADG428/ADG429. TERMINOLOGY. ADG428 Truth Table. WR RS. ON SWITCH. ADG429 Truth Table. ON SWITCH PAIR
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Text Version of Document
ADG428/ADG429 TERMINOLOGY ADG428 Truth Table
VDD Most positive power supply potential.
A2 A1 A0 EN WR RS ON SWITCH
VSS Most negative power supply potential in dual Latching supplies. In single supply applications, it may be connected to ground. X X X X g 1 Maintains Previous Switch Condition GND Ground (0 V) reference. Reset RON Ohmic resistance between D and S. X X X X X 0 NONE ∆RON Difference between the RON of any two (Latches Cleared) channels. I Transparent Operation S (OFF) Source leakage current when the switch is off. ID (OFF) Drain leakage current when the switch is off. X X X 0 0 1 NONE 0 0 0 1 0 1 1 ID, IS (ON) Channel leakage current when the switch is 0 0 1 1 0 1 2 on. 0 1 0 1 0 1 3 VD (VS) Analog voltage on terminals D, S. 0 1 1 1 0 1 4 CS (OFF) Channel input capacitance for “OFF” 1 0 0 1 0 1 5 condition. 1 0 1 1 0 1 6 1 1 0 1 0 1 7 CD (OFF) Channel output capacitance for “OFF” 1 1 1 1 0 1 8 condition. CD, CS (ON) “ON” switch capacitance.
ADG429 Truth Table
CIN Digital input capacitance.
A1 A0 EN WR RS ON SWITCH PAIR
tON (EN) Delay time between the 50% and 90% points of the digital input and switch “ON” Latching condition. X X X g 1 Maintains Previous tOFF (EN) Delay time between the 50% and 90% points Switch Condition of the digital input and switch “OFF” condition. Reset tTRANSITlON Delay time between the 50% and 90% points X X X X 0 NONE of the digital inputs and the switch “ON” (Latches Cleared) condition when switching from one address Transparent Operation state to another. X X 0 0 1 NONE tOPEN “OFF” time measured between 80% points of 0 0 1 0 1 1 both switches when switching from one 0 1 1 0 1 2 address state to another. 1 0 1 0 1 3 VINL Maximum input voltage for Logic “0.” 1 1 1 0 1 4 VINH Minimum input voltage for Logic “1.” IINL (IINH) Input current of the digital input. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an “OFF” channel. Charge A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching. IDD Positive supply current. ISS Negative supply current. REV. C –5–
VDD Most positive power supply potential.
A2 A1 A0 EN WR RS ON SWITCH
VSS Most negative power supply potential in dual Latching supplies. In single supply applications, it may be connected to ground. X X X X g 1 Maintains Previous Switch Condition GND Ground (0 V) reference. Reset RON Ohmic resistance between D and S. X X X X X 0 NONE ∆RON Difference between the RON of any two (Latches Cleared) channels. I Transparent Operation S (OFF) Source leakage current when the switch is off. ID (OFF) Drain leakage current when the switch is off. X X X 0 0 1 NONE 0 0 0 1 0 1 1 ID, IS (ON) Channel leakage current when the switch is 0 0 1 1 0 1 2 on. 0 1 0 1 0 1 3 VD (VS) Analog voltage on terminals D, S. 0 1 1 1 0 1 4 CS (OFF) Channel input capacitance for “OFF” 1 0 0 1 0 1 5 condition. 1 0 1 1 0 1 6 1 1 0 1 0 1 7 CD (OFF) Channel output capacitance for “OFF” 1 1 1 1 0 1 8 condition. CD, CS (ON) “ON” switch capacitance.
ADG429 Truth Table
CIN Digital input capacitance.
A1 A0 EN WR RS ON SWITCH PAIR
tON (EN) Delay time between the 50% and 90% points of the digital input and switch “ON” Latching condition. X X X g 1 Maintains Previous tOFF (EN) Delay time between the 50% and 90% points Switch Condition of the digital input and switch “OFF” condition. Reset tTRANSITlON Delay time between the 50% and 90% points X X X X 0 NONE of the digital inputs and the switch “ON” (Latches Cleared) condition when switching from one address Transparent Operation state to another. X X 0 0 1 NONE tOPEN “OFF” time measured between 80% points of 0 0 1 0 1 1 both switches when switching from one 0 1 1 0 1 2 address state to another. 1 0 1 0 1 3 VINL Maximum input voltage for Logic “0.” 1 1 1 0 1 4 VINH Minimum input voltage for Logic “1.” IINL (IINH) Input current of the digital input. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an “OFF” channel. Charge A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching. IDD Positive supply current. ISS Negative supply current. REV. C –5–
