Datasheet ADG854 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 0.5 Ω CMOS, 1.8 V to 5.5 V, Dual SPDT/2:1 Mux, Mini LFCSP |
| Pages / Page | 16 / 10 — ADG854. TEST CIRCUITS. IS (OFF). ID (OFF). IDS. ID (ON). RON = V1/IDS. … |
| File Format / Size | PDF / 303 Kb |
| Document Language | English |
ADG854. TEST CIRCUITS. IS (OFF). ID (OFF). IDS. ID (ON). RON = V1/IDS. VDD. 0.1µF. S1B. 50%. S1A. OUT. VIN. 50Ω. 35pF. 90%. VOUT. GND. tOFF. 80%. tBBM. SW ON. SW OFF
Model Line for this Datasheet
Text Version of Document
ADG854 TEST CIRCUITS IS (OFF) ID (OFF) S D A A IDS VS VD
20 0
V1
7- 08 07 Figure 17. Off Leakage
S D ID (ON) S D NC V
9
A
1
S RON = V1/IDS
01 02 7-
VD
7- 08 08 07 07 Figure 16. On Resistance Figure 18. On Leakage
VDD 0.1µF VDD V S1B S V 50% 50% S1A D OUT VIN RL CL IN 50Ω 35pF 90% 90% VOUT GND
22 0
t
7-
ON tOFF
7080 Figure 19. Switching Times, tON, tOFF
VDD 0.1µF 50% 50% V 0V DD VIN V S1B S V V OUT OUT S1A D 80% 80% RL CL IN 50Ω 35pF tBBM tBBM GND
23 0 7- 08 07 Figure 20. Break-Before-Make Time Delay, tBBM
VDD SW ON SW OFF VIN S1B NC D VS S1A VOUT IN 1nF VOUT ΔVOUT GND QINJ = CL × ΔVOUT
24 0 7- 08 07 Figure 21. Charge Injection Rev. 0 | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTION TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
20 0
V1
7- 08 07 Figure 17. Off Leakage
S D ID (ON) S D NC V
9
A
1
S RON = V1/IDS
01 02 7-
VD
7- 08 08 07 07 Figure 16. On Resistance Figure 18. On Leakage
VDD 0.1µF VDD V S1B S V 50% 50% S1A D OUT VIN RL CL IN 50Ω 35pF 90% 90% VOUT GND
22 0
t
7-
ON tOFF
7080 Figure 19. Switching Times, tON, tOFF
VDD 0.1µF 50% 50% V 0V DD VIN V S1B S V V OUT OUT S1A D 80% 80% RL CL IN 50Ω 35pF tBBM tBBM GND
23 0 7- 08 07 Figure 20. Break-Before-Make Time Delay, tBBM
VDD SW ON SW OFF VIN S1B NC D VS S1A VOUT IN 1nF VOUT ΔVOUT GND QINJ = CL × ΔVOUT
24 0 7- 08 07 Figure 21. Charge Injection Rev. 0 | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTION TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
