Datasheet ADG824 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 0.5 Ω CMOS 1.65 V to 3.6 V Dual SPDT/2:1 Mux in Mini LFCSP Package |
| Pages / Page | 16 / 5 — Data Sheet. ADG824. Table 3. Parameter. +25°C. −40°C to +85°C. Unit. Test … |
| Revision | C |
| File Format / Size | PDF / 243 Kb |
| Document Language | English |
Data Sheet. ADG824. Table 3. Parameter. +25°C. −40°C to +85°C. Unit. Test Conditions/Comments
Model Line for this Datasheet
Text Version of Document
link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 12 link to page 12 link to page 12 link to page 12 link to page 12 link to page 8 link to page 5
Data Sheet ADG824
VDD = 1.65 V to 1.95 V, GND = 0 V, unless otherwise noted.
Table 3. Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 1.3 Ω typ VDD = 1.8 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19 2 2.4 Ω max 3.1 3.6 Ω max VDD = 1.65 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19 On Resistance Match Between 0.01 Ω typ VDD = 1.65 V, VS = 0.7 V, IDS = 100 mA Channels, ∆RON LEAKAGE CURRENTS VDD = 1.95 V Source Off Leakage, IS (Off) ±0.2 nA typ VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V; see Figure 20 Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 0.6 V or 1.65 V; see Figure 21 DIGITAL INPUTS Input High Voltage, VINH 0.65 VDD V min Input Low Voltage, VINL 0.35 VDD V max Input Current IINL or IINH 0.005 µA typ VIN = VGND or VDD ±0.1 µA max VIN = VGND or VDD Digital Input Capacitance, CIN 2.7 pF typ DYNAMIC CHARACTERISTICS1 tON 13 ns typ RL = 50 Ω, CL = 35 pF 18.6 19.3 ns max VS = 1.2 V/0 V; see Figure 22 tOFF 7 ns typ RL = 50 Ω, CL = 35 pF 9.8 10.2 ns max VS = 1.2 V; see Figure 22 Break-Before-Make Time Delay, tBBM 7.5 ns typ RL = 50 Ω, CL = 35 pF 5 ns min VS1 = VS2 = 1.2 V; see Figure 23 Charge Injection, QINJ 15 pC typ VS = 1 V, RS = 0 Ω, CL = 1 nF; see Figure 24 Off Isolation −71 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 Channel-to-Channel Crosstalk −90 dB typ S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26 −71 dB typ S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 Total Harmonic Distortion, THD + N 0.4 % RL = 33 Ω, f = 20 Hz to 20 kHz, VS = 1.2 V p-p Insertion Loss −0.1 dB typ RL = 50 Ω, CL = 5 pF; see Figure 28 –3 dB Bandwidth 90 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28 CS (Off) 26 pF typ CD, CS (On) 61 pF typ POWER REQUIREMENTS VDD = 1.95 V IDD 0.003 µA typ Digital inputs = 0 V or 1.95 V 1 µA max 1 Guaranteed by design; not subject to production test. Rev. C | Page 5 of 16 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Outline Dimensions Ordering Guide
Data Sheet ADG824
VDD = 1.65 V to 1.95 V, GND = 0 V, unless otherwise noted.
Table 3. Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 1.3 Ω typ VDD = 1.8 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19 2 2.4 Ω max 3.1 3.6 Ω max VDD = 1.65 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 19 On Resistance Match Between 0.01 Ω typ VDD = 1.65 V, VS = 0.7 V, IDS = 100 mA Channels, ∆RON LEAKAGE CURRENTS VDD = 1.95 V Source Off Leakage, IS (Off) ±0.2 nA typ VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V; see Figure 20 Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 0.6 V or 1.65 V; see Figure 21 DIGITAL INPUTS Input High Voltage, VINH 0.65 VDD V min Input Low Voltage, VINL 0.35 VDD V max Input Current IINL or IINH 0.005 µA typ VIN = VGND or VDD ±0.1 µA max VIN = VGND or VDD Digital Input Capacitance, CIN 2.7 pF typ DYNAMIC CHARACTERISTICS1 tON 13 ns typ RL = 50 Ω, CL = 35 pF 18.6 19.3 ns max VS = 1.2 V/0 V; see Figure 22 tOFF 7 ns typ RL = 50 Ω, CL = 35 pF 9.8 10.2 ns max VS = 1.2 V; see Figure 22 Break-Before-Make Time Delay, tBBM 7.5 ns typ RL = 50 Ω, CL = 35 pF 5 ns min VS1 = VS2 = 1.2 V; see Figure 23 Charge Injection, QINJ 15 pC typ VS = 1 V, RS = 0 Ω, CL = 1 nF; see Figure 24 Off Isolation −71 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 Channel-to-Channel Crosstalk −90 dB typ S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26 −71 dB typ S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 Total Harmonic Distortion, THD + N 0.4 % RL = 33 Ω, f = 20 Hz to 20 kHz, VS = 1.2 V p-p Insertion Loss −0.1 dB typ RL = 50 Ω, CL = 5 pF; see Figure 28 –3 dB Bandwidth 90 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28 CS (Off) 26 pF typ CD, CS (On) 61 pF typ POWER REQUIREMENTS VDD = 1.95 V IDD 0.003 µA typ Digital inputs = 0 V or 1.95 V 1 µA max 1 Guaranteed by design; not subject to production test. Rev. C | Page 5 of 16 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Outline Dimensions Ordering Guide
