Datasheet Si1308EDL (Vishay) - 9

AN813 Vishay Siliconix
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
SC-70 (6-PIN)
(the Package Performance) Room Ambient 25
_
C Elevated Ambient 60
_
C
Thermal performance for the 3-pin SC-70 measured as junction-to-foot thermal resistance is 285_C/W typical, T T J(max) * TA J(max) * TA 340 P _C/W maximum. Junction-to-foot thermal resistance for PD + Rq D + Rq JA JA the 6-pin SC70-6 is 105_C/W typical, 130_C/W maximum — a nearly two-thirds reduction compared with the 3-pin device. PD + 150oC * 25oC 180oCńW PD + 150oC * 60oC 180oCńW The “foot” is the drain lead of the device as it connects with the body. This improved performance is obtained by the increase PD + 694 mW PD + 500 mW in drain leads from one to four on the 6-pin SC-70. Note that these numbers are somewhat higher than other LITTLE FOOT NOTE: Although they are intended for low-power applications, devices due to the limited thermal performance of the Alloy 42 devices in the 6-pin SC-70 will handle power dissipation in lead-frame compared with a standard copper lead-frame. excess of 0.5 W.
Testing Junction-to-Ambient Thermal Resistance (dependent on PCB size)
To aid comparison further, Figures 3 and 4 illustrate single-channel SC-70 thermal performance on two different The typical Rθ board sizes and two different pad patterns. The results display JAfor the single 3-pin SC-70 is 360_C/W steady state, compared with 180_C/W for the 6-pin SC-70. Maximum the thermal performance out to steady state and produce a ratings are 430_C/W for the 3-pin device versus 220_C/W for graphic account of the thermal performance variation between the 6-pin device. All figures are based on the 1-inch square the two packages. The measured steady state values of RθJA FR4 test board.The following table shows how the thermal for the single 3-pin and 6-pin SC-70 are as follows: resistance impacts power dissipation for the two different pin-outs at two different ambient temperatures. LITTLE FOOT SC-70
3-Pin 6-Pin
SC-70 (3-PIN) 1) Minimum recommended pad pattern (see Figure 4) on the EVB. 410.31_C/W 329.7_C/W
Room Ambient 25
_
C Elevated Ambient 60
_
C
2) Industry standard 1” square PCB with maximum copper both sides. 360_C/W 211.8_C/W T P J(max) * TA TJ(max) * TA The results show that designers can reduce thermal D + Rq P JA D + RqJA resistance RθJA on the order of 20% simply by using the 6-pin P device rather than the 3-pin device. In this example, a 80_C/W D + 150oC * 25oC 360oCńW PD + 150oC * 60oC 360oCńW reduction was achieved without an increase in board area. If increasing board size is an option, a further 118_C/W reduction P P D + 347 mW D + 250 mW could be obtained by utilizing a 1-inch square PCB area. 400 400 320 320 3-pin 3-pin 240 240 6-pin 6-pin 160 160 Thermal Resistance (C/W) Thermal Resistance (C/W) 80 80 0.5 in x 0.6 in EVB 1” Square FR4 PCB 0 0 10-1 10-2 10-3 10-4 10-5 1 10 100 1000 10-1 10-2 10-3 10-4 10-5 1 10 100 1000 Time (Secs) Time (Secs)
FIGURE 3.
Comparison of SC70-3 and SC70-6 on EVB
FIGURE 4.
Comparison of SC70-3 and SC70-6 on 1” Square FR4 PCB www.vishay.com Document Number: 71236
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12-Dec-03