Datasheet AD9731 (Analog Devices) - 9

AD9731 THEORY AND APPLICATIONS References
The AD9731 high speed digital-to-analog converter utilizes The internal band gap reference, control amplifier, and refer- most significant bit decoding and segmentation techniques to ence input are pinned out to provide maximum user flexibility reduce glitch impulse and deliver high dynamic performance in configuring the reference circuitry for the AD9731. When on lower power consumption than previous bipolar DAC using the internal reference, REF OUT (Pin 25) should be con- technologies. nected to CONTROL AMP IN (Pin 26). CONTROL AMP OUT The design is based on four main subsections: the decoder/ (Pin 24) should be connected to REF IN (Pin 23). A 0.1 mF driver circuits, the edge-triggered data register, the switch net- ceramic capacitor connected from Pin 23 to Analog –VS (Pin 22) work, and the control amplifier. An internal band gap reference improves settling time by decoupling switching noise from the is included to allow operation of the device with minimum current sink baseline. A reference current cell provides feedback external support components. to the control amplifier by sinking current through RSET (Pin 17).
Digital Inputs/Timing
Full-scale current is determined by CONTROL AMP IN and The AD9731 has TTL/high speed CMOS-compatible single-ended RSET according to the following equation: inputs for data inputs and clock. The switching threshold is 1.5 V. IOUT (FS) = 32(CONTROL AMP IN/RSET) In the decoder/driver section, the three MSBs are decoded to The internal reference is nominally –1.25 V with a tolerance of seven “thermometer code” lines. An equalizing delay is included ±8% and typical drift over temperature of 100 ppm/∞C. If for the seven least significant bits and the clock signals. This greater accuracy or temperature stability is required, an external
OBSOLETE
delay minimizes data skew and data setup and hold times at the reference can be used. The AD589 reference features 10 ppm/∞C register inputs. drift over the 0∞C to 70∞C temperature range. The on-board register is rising edge triggered and should be Two modes of multiplying operation are possible with the used to synchronize data to the current switches by applying a AD9731. Signals with bandwidths up to 2.5 MHz and input pulse with proper data setup and hold times as shown in the swings from –0.6 V to –1.2 V can be applied to the CONTROL timing diagram. Although the AD9731 is designed to provide AMP IN pin as shown in Figure 3. Because the control ampli- isolation of the digital inputs to the analog output, some cou- fier is internally compensated, the 0.1 mF capacitor discussed pling of digital transitions is inevitable. Digital feedthrough can above can be reduced to maximize the multiplying bandwidth. be minimized by forming a low pass filter at the digital input by However, it should be noted that output settling time, for using a resistor in series with the capacitance of each digital changes in the digital word, will be degraded. input. This common high speed DAC application technique has the effect of isolating digital input noise from the analog output.
AD9731 Input Clock and Data Timing Relationship RSET
SINAD in a DAC is dependent on the relationship between the
RSET
position of the clock edges and the point in time at which the input data changes. The AD9731 is rising edge triggered, and so
–0.6 TO –1.2V CONTROL
exhibits SINAD sensitivity when the data transition is close to
2.5MHz TYPICAL AMP IN R
this edge. In general, the goal when applying the AD9731 is to
T
make the data transition close to the falling clock edge. This
CONTROL
becomes more important as the sample rate increases. Figure 2
AMP OUT
shows the relationship of SINAD to clock placement from the AD9731 and a competitive part, both sampling at 125 MSPS.
REFERENCE IN
The AD9731 has excellent performance as far as the narrowness of the “window” in which it is sensitive to SINAD.
0.1
␮
F 60 AD9731 ANALOG –VS 50
Figure 3. Low Frequency Multiplying Circuit
40 COMPETITION 30 SINAD – dB 20 10 0 –4 –3 –2 –1 0 1 2 3 4 TIME OF DATA PLACEMENT RELATIVE TO RISING EDGE OF CLOCK – ns
Figure 2. SINAD vs. Clock Placement; fCLK = 125 MSPS, fOUT = 20 MHz REV. B –9– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION Typical Performance Characteristics THEORY AND APPLICATIONS Digital Inputs/Timing Input Clock and Data Timing Relationship References Analog Output EVALUATION BOARD OUTLINE DIMENSIONS Revision History