Datasheet ADP3051 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 500 mA PWM Step-Down DC-DC with Synchronous Rectifier |
| Pages / Page | 16 / 9 — ADP3051. THEORY OF OPERATION. TRI-MODE OPERATION. PWM CONTROL MODE. 4 IN. … |
| File Format / Size | PDF / 441 Kb |
| Document Language | English |
ADP3051. THEORY OF OPERATION. TRI-MODE OPERATION. PWM CONTROL MODE. 4 IN. SHDN 7. CONTROL. VOLTAGE. UVLO. FREQUENCY. LOGIC. REFERENCE. FOLDBACK
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ADP3051 THEORY OF OPERATION
The ADP3051 is a monolithic current mode buck converter COMP, which sets inductor peak current. The error amplifier, with an integrated high-side switch and low-side synchronous and thus the output voltage, controls the inductor peak current rectifier. It operates with input voltages between 2.7 V and 5.5 V, to regulate the output voltage. An internally generated slope regulates an output voltage down to 0.8 V, and supplies more compensation circuit ensures that the inner current control than 500 mA of load current. The ADP3051 features patented loop maintains stable operation over the entire input and output Tri-Mode technology to operate in fixed frequency PWM mode voltage range. at medium to heavy loads. This improves light-load efficiency
TRI-MODE OPERATION
by smoothly transitioning into a variable frequency PWM mode, and into a single-pulse, current-limited variable The ADP3051 features patented Tri-Mode technology which frequency mode at very light loads. allows fixed-frequency, current mode, PWM operation at medium and heavy loads; smoothly transitions to variable
PWM CONTROL MODE
frequency PWM operation to improve light-load efficiency; and At moderate to high output currents, the ADP3051 operates operates in a single-pulse, current-limited variable frequency in a fixed frequency, peak current control mode to regulate the mode at very light loads. These three modes work together to output voltage. At the beginning of each cycle, the P-channel provide high efficiency over a wide range of load current condi- output switch turns on and remains on until the inductor cur- tions without the frequency jitter, increased output voltage rent exceeds the threshold set by the voltage at COMP. When ripple, and audible noise generation exhibited by other light- the P-channel switch turns off, the N-channel synchronous load control schemes. rectifier turns on for the remainder of the cycle, after which the cycle repeats. The ADP3051’s internal oscillator is a key component of its Tri-Mode operation. Under medium-heavy load conditions, the In current mode, two cascaded control loops combine to regu- oscillator operates at a constant 550 kHz. Under light-load late the output voltage. The outer voltage control loop senses the conditions, the oscillator frequency is decreased to minimize voltage at FB and compares it to the internal 0.8 V reference. switching losses, thus improving light-load efficiency. At very The internal transconductance amplifier forces a current at light loads, the oscillator is disabled and the ADP3051 switches COMP proportional to the voltage difference between the refer- only as required to supply the load current for good light-load ence and FB. By selecting the components between COMP and efficiency. GND, the frequency characteristics of the control system give a stable regulation system. In addition to Tri-Mode operation, the ADP3051 operates in the 200 kHz frequency foldback mode when the voltage at FB is The inner peak-current control loop monitors the current flow- below 0.3 V for enhanced control of the inductor current under ing through the P-channel MOSFET and converts that to a short-circuit and startup conditions. See the Short-Circuit Pro- voltage. This voltage is internally compared to the voltage at tection and Recovery section.
4 IN SHDN 7 CONTROL VOLTAGE UVLO FREQUENCY LOGIC REFERENCE FOLDBACK CURRENT 0.4V COMPARATOR SENSE OSCILLATOR PWM COMPARATOR COMP GATE 6 3 SW S Q DRIVERS ERROR AMPLIFIER R FB 5 gm ADP3051 2 PGND 0.8V 1 8 NC GND
04768-0-016 Figure 17. Simplified Block Diagram Rev. 0 | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIP TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM CONTROL MODE TRI-MODE OPERATION 100% DUTY CYCLE OPERATION SHUTDOWN UNDERVOLTAGE LOCKOUT (UVLO) SHORT-CIRCUIT PROTECTION AND RECOVERY APPLICATIONS RECOMMENDED COMPONENTS DESIGN PROCEDURE Setting the Output Voltage Inductor Selection OUTPUT CAPACITOR SELECTION Input Capacitor Selection Compensation Design CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
ADP3051 THEORY OF OPERATION
The ADP3051 is a monolithic current mode buck converter COMP, which sets inductor peak current. The error amplifier, with an integrated high-side switch and low-side synchronous and thus the output voltage, controls the inductor peak current rectifier. It operates with input voltages between 2.7 V and 5.5 V, to regulate the output voltage. An internally generated slope regulates an output voltage down to 0.8 V, and supplies more compensation circuit ensures that the inner current control than 500 mA of load current. The ADP3051 features patented loop maintains stable operation over the entire input and output Tri-Mode technology to operate in fixed frequency PWM mode voltage range. at medium to heavy loads. This improves light-load efficiency
TRI-MODE OPERATION
by smoothly transitioning into a variable frequency PWM mode, and into a single-pulse, current-limited variable The ADP3051 features patented Tri-Mode technology which frequency mode at very light loads. allows fixed-frequency, current mode, PWM operation at medium and heavy loads; smoothly transitions to variable
PWM CONTROL MODE
frequency PWM operation to improve light-load efficiency; and At moderate to high output currents, the ADP3051 operates operates in a single-pulse, current-limited variable frequency in a fixed frequency, peak current control mode to regulate the mode at very light loads. These three modes work together to output voltage. At the beginning of each cycle, the P-channel provide high efficiency over a wide range of load current condi- output switch turns on and remains on until the inductor cur- tions without the frequency jitter, increased output voltage rent exceeds the threshold set by the voltage at COMP. When ripple, and audible noise generation exhibited by other light- the P-channel switch turns off, the N-channel synchronous load control schemes. rectifier turns on for the remainder of the cycle, after which the cycle repeats. The ADP3051’s internal oscillator is a key component of its Tri-Mode operation. Under medium-heavy load conditions, the In current mode, two cascaded control loops combine to regu- oscillator operates at a constant 550 kHz. Under light-load late the output voltage. The outer voltage control loop senses the conditions, the oscillator frequency is decreased to minimize voltage at FB and compares it to the internal 0.8 V reference. switching losses, thus improving light-load efficiency. At very The internal transconductance amplifier forces a current at light loads, the oscillator is disabled and the ADP3051 switches COMP proportional to the voltage difference between the refer- only as required to supply the load current for good light-load ence and FB. By selecting the components between COMP and efficiency. GND, the frequency characteristics of the control system give a stable regulation system. In addition to Tri-Mode operation, the ADP3051 operates in the 200 kHz frequency foldback mode when the voltage at FB is The inner peak-current control loop monitors the current flow- below 0.3 V for enhanced control of the inductor current under ing through the P-channel MOSFET and converts that to a short-circuit and startup conditions. See the Short-Circuit Pro- voltage. This voltage is internally compared to the voltage at tection and Recovery section.
4 IN SHDN 7 CONTROL VOLTAGE UVLO FREQUENCY LOGIC REFERENCE FOLDBACK CURRENT 0.4V COMPARATOR SENSE OSCILLATOR PWM COMPARATOR COMP GATE 6 3 SW S Q DRIVERS ERROR AMPLIFIER R FB 5 gm ADP3051 2 PGND 0.8V 1 8 NC GND
04768-0-016 Figure 17. Simplified Block Diagram Rev. 0 | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIP TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM CONTROL MODE TRI-MODE OPERATION 100% DUTY CYCLE OPERATION SHUTDOWN UNDERVOLTAGE LOCKOUT (UVLO) SHORT-CIRCUIT PROTECTION AND RECOVERY APPLICATIONS RECOMMENDED COMPONENTS DESIGN PROCEDURE Setting the Output Voltage Inductor Selection OUTPUT CAPACITOR SELECTION Input Capacitor Selection Compensation Design CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
