Datasheet TPLD1201 (Texas Instruments) - 6

link to page 8
TPLD1201
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
www.ti.com
over operating free-air temperature range (unless otherwise noted)
TEST PARAMETER V CONDITIONS CC MIN TYP MAX UNIT
Push-pull 1X or Open- 1.68 drain PMOS 1X IOH = -100µA 1.8V ± 0.09V Push-pull 2X or Open- 1.69 drain PMOS 2X Push-pull 1X or Open- 2.60 drain PMOS 1X VOH High-level output voltage IOH = -3mA 3.3V ± 0.3V V Push-pull 2X or Open- 2.71 drain PMOS 2X Push-pull 1X or Open- 3.99 drain PMOS 1X IOH = -5mA 5V ± 0.5V Push-pull 2X or Open- 4.13 drain PMOS 2X Push-pull 1X 0.038 Push-pull 2X 0.034 IOL = 100µA 1.8V ± 0.09V Open-drain NMOS 1X 0.045 Open-drain NMOS 2X 0.02 Push-pull 1X 0.1 Push-pull 2X 0.1 VOL Low-level output voltage IOL = 3mA 3.3V ± 0.3V V Open-drain NMOS 1X 0.1 Open-drain NMOS 2X 0.1 Push-pull 1X 0.12 Push-pull 2X 0.12 IOL = 5mA 5V ± 0.5V Open-drain NMOS 1X 0.12 Open-drain NMOS 2X 0.12 VI = VCC 1.65V to 5.5V ±1 II Input leakage current All pins µA VI = GND 1.65V to 5.5V ±1 Off-state (high-Z state) IOZ IO1, IO2, IO5, IO6, IO9 V output current O = 0 to 5.5V 0.06 µA 1.8V ± 0.09V 5 15pF Load FOUT Max output frequency(1) Push-pull 1X or Push-pull 3.3V ± 0.3V 12 MHz 2X capacitance 5V ± 0.5V 12 1 MΩ Rpu(int) Internal pull-up resistance 100 kΩ 10 kΩ 1 MΩ Rpd(int) Internal pull-down resistance 100 kΩ 10 kΩ CI Input pin capacitance each input pin VI = VCC or GND 1.71V to 5.5V 1.2 pF Input-output pin V C IO = VCC or IO each I/O pin 1.71V to 5.5V 2.0 pF capacitance GND
Analog Comparator
ACMP power on Bandgap always tstart Start time 1.71V to 5.5V 130 µs delay on Positive input 0 VCC VAI Input voltage 1.71V to 5.5V V Negative input 0 1.2 6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data