Datasheet TPLD1201 (Texas Instruments) - 9

TPLD1201 www.ti.com
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
5.7 Switching Characteristics
TA = 25°C (unless otherwise noted)
FROM TO TEST PARAMETER V (INPUT) (OUTPUT) CONDITIONS CC MIN TYP MAX UNIT Digital IO
Rising 46.2 1.8V ± 0.09V Falling 39.1 Push-pull Rising 27.2 tpd Delay Digital input 3.3V ± 0.3V ns output Falling 24.5 Rising 22.1 5V ± 0.5V Falling 21.1 Rising 49.5 1.8V ± 0.09V Falling 41.5 Digital input Push-pull Rising 29.3 tpd Delay with Schmitt 3.3V ± 0.3V ns output trigger Falling 25.3 Rising 23.9 5V ± 0.5V Falling 21.5 Rising 45.0 1.8V ± 0.09V Falling 48.1 Low-voltage Push-pull Rising 25.4 tpd Delay 3.3V ± 0.3V ns digital input output Falling 30.3 Rising 19.6 5V ± 0.5V Falling 28.6 Rising 1.8V ± 0.09V Falling 38.8 Open-drain Rising tpd Delay Digital input 3.3V ± 0.3V ns NMOS output Falling 24.3 Rising 5V ± 0.5V Falling 20.9 1.8V ± 0.09V 45.0 Hi-Z to 1 1.8V ± 0.09V 26.5 ns Output enable Push-pull 3.3V ± 0.3V 21.7 tpd Delay OE from pin output 3.3V ± 0.3V 43.2 Hi-Z to 0 5V ± 0.5V 22.6 ns 5V ± 0.5V 18.3
Configurable Use Logic
Rising 1.14 1.8V ± 0.09V Falling 1.32 Rising 1.14 tpd Delay 2-bit LUT IN OUT 3.3V ± 0.3V ns Falling 1.31 Rising 1.16 5V ± 0.5V Falling 1.35 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPLD1201 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data