Datasheet HEF4013B (Nexperia) - 7
| Manufacturer | Nexperia |
| Description | Dual D-Type Flip-Flop |
| Pages / Page | 14 / 7 — Nexperia. HEF4013B. Dual D-type flip-flop. Symbol Parameter. Conditions. … |
| File Format / Size | PDF / 253 Kb |
| Document Language | English |
Nexperia. HEF4013B. Dual D-type flip-flop. Symbol Parameter. Conditions. VDD. Extrapolation formula. Min. Typ Max Unit
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Nexperia HEF4013B Dual D-type flip-flop Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
trec recovery time nSD input; see Fig. 4 5 V +15 -5 - ns 10 V 15 0 - ns 15 V 15 0 - ns nCD input; see Fig. 4 5 V 40 25 - ns 10 V 25 10 - ns 15 V 25 10 - ns fclk(max) maximum clock see Fig. 3 5 V 7 14 - MHz frequency 10 V 14 28 - MHz 15 V 20 40 - MHz [1] Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas (CL in pF).
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula Where
PD dynamic power dissipation 5 V PD = 850 × fi + Σ(fo × CL) × VDD 2 μW fi = input frequency in MHz; 10 V P f D = 3600 × fi + Σ(fo × CL) × VDD 2 μW o = output frequency in MHz; CL = output load capacitance in pF; 15 V PD = 9000 × fi + Σ(fo × CL) × VDD 2 μW Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V.
11.1. Waveforms and test circuit
1/fclk(max) tW VI input nCP VM 0 V tsu tsu tf tr th th VI input nD VM 0 V tPLH tPHL tt tt VOH VY output nQ VM V V OL X 001aah016 Set-up and hold times are shown as positive values but may be specified as negative values. The shaded areas indicate when the input is permitted to change for predictable output performance. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 9.
Fig. 3. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. Al rights reserved
Product data sheet Rev. 12 — 24 July 2024 7 / 14
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1. Pinning 6.2. Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1. Waveforms and test circuit 12. Application information 13. Package outline 14. Abbreviations 15. Revision history 16. Legal information Contents
Nexperia HEF4013B Dual D-type flip-flop Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
trec recovery time nSD input; see Fig. 4 5 V +15 -5 - ns 10 V 15 0 - ns 15 V 15 0 - ns nCD input; see Fig. 4 5 V 40 25 - ns 10 V 25 10 - ns 15 V 25 10 - ns fclk(max) maximum clock see Fig. 3 5 V 7 14 - MHz frequency 10 V 14 28 - MHz 15 V 20 40 - MHz [1] Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas (CL in pF).
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula Where
PD dynamic power dissipation 5 V PD = 850 × fi + Σ(fo × CL) × VDD 2 μW fi = input frequency in MHz; 10 V P f D = 3600 × fi + Σ(fo × CL) × VDD 2 μW o = output frequency in MHz; CL = output load capacitance in pF; 15 V PD = 9000 × fi + Σ(fo × CL) × VDD 2 μW Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V.
11.1. Waveforms and test circuit
1/fclk(max) tW VI input nCP VM 0 V tsu tsu tf tr th th VI input nD VM 0 V tPLH tPHL tt tt VOH VY output nQ VM V V OL X 001aah016 Set-up and hold times are shown as positive values but may be specified as negative values. The shaded areas indicate when the input is permitted to change for predictable output performance. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 9.
Fig. 3. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. Al rights reserved
Product data sheet Rev. 12 — 24 July 2024 7 / 14
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1. Pinning 6.2. Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1. Waveforms and test circuit 12. Application information 13. Package outline 14. Abbreviations 15. Revision history 16. Legal information Contents
