Datasheet AD9625 (Analog Devices) - 12

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AD9625 Data Sheet Pin No. Mnemonic Type Description
F11 AVDD2 Power ADC Analog Power Supply (2.50 V). F12 AVDD1 Power ADC Analog Power Supply (1.30 V). F13 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane. F14 CLK+ Input ADC Clock Input, True. G1 to G3 DGND Ground Digital Control Ground Supply. These pins connect to the digital ground plane. G4 CSB Input SPI Chip Select CMOS Input. Active low. G5 DVDDIO Power Digital I/O Power Supply (2.50 V). G6 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane. G7 AVDD1 Power ADC Analog Power Supply (1.30 V). G8 AVDD2 Power ADC Analog Power Supply (2.50 V). G9, G10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane. G11 AVDD2 Power ADC Analog Power Supply (2.50 V). G12 AVDD1 Power ADC Analog Power Supply (1.30 V). G13 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane. G14 CLK− Input ADC Clock Input, Complement. H1 to H3 DVDD1 Power ADC Digital Power Supply (1.30 V). H4 SCLK Input SPI Serial Clock CMOS Input. H5 IRQ Output Interrupt Request Output Signal. H6 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane. H7 AVDD1 Power ADC Analog Power Supply (1.30 V). H8 AVDD2 Power ADC Analog Power Supply (2.50 V). H9, H10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane. H11 AVDD2 Power ADC Analog Power Supply (2.50 V). H12 AVDD1 Power ADC Analog Power Supply (1.30 V). H13, H14 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane. J1 to J3 DGND Ground Digital Control Ground Supply. These pins connect to the digital ground plane. J4 SDIO I/O SPI Serial Data CMOS Input/Output; Scan Output 1. J5 FD Output Fast Detect Output. This pin requires an external 10 kΩ resistor connected to ground. J6 RBIAS_EXT Input Reference Bias. This pin requires an external 10 kΩ resistor connected to ground. J7 AVDD1 Power ADC Analog Power Supply (1.30 V). J8 AVDD2 Power ADC Analog Power Supply (2.50 V). J9, J10 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane. J11 AVDD2 Power ADC Analog Power Supply (2.50 V). J12 AVDD1 Power ADC Analog Power Supply (1.30 V). J13 AGND Ground ADC Analog Ground. This pin connects to the analog ground plane. J14 SYSREF+ Input System Reference Chip Synchronization, True. K1 to K2 DVDD1 Power ADC Digital Power Supply (1.30 V). K3 RSTB Input Chip Digital Reset, Active Low. K4 PWDN Input Power-down. K5 to K13 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane. K14 SYSREF− Input System Reference Chip Synchronization, Complement. L1 DGND Ground Digital Control Ground Supply. This pin connects to the digital ground plane. L2 DNC N/A1 Do Not Connect. Do not connect to this pin. Leave this pin floating. L3 SYNCINB− Input Synchronization, Complement. L4 SYNCINB+ Input Synchronization, True. SYNCINB LVDS input (active low, true). L5 to L9 DGND Ground Digital Control Ground Supply. These pins connect to the digital ground plane. L10 to L12 DNC N/A1 Do Not Connect. Do not connect to these pins. Leave these pins floating. L13, L14 AGND Ground ADC Analog Ground. These pins connect to the analog ground plane. M1 to M10 DRGND Ground Digital Driver Ground Supply. These pins connect to the digital driver ground plane. M11 DRVDD1 Power Power Supply (1.3 V) Reference Clock Divider, VCO, and Synthesizer. M12 REXT Input External Resistor, 10 kΩ to Ground. M13, M14 DRGND Ground Digital Driver Ground Supply. This pin connects to the digital driver ground plane. Rev. B | Page 12 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE