Fujitsu Semiconductor has developed a new manufacturing technology "CS250S". It is the implementation of the Deeply Depleted Channel™ (DDC) technology, licensed by SuVolta, Inc., using the 55 nm process technology of Mie Plant. DDC enables a significant power reduction while utilizing a conventional planar CMOS structure and CS250S is the world's first successful application of the technology into the actual volume production.
In order to reduce the power consumption of CMOS circuits, it is necessary to reduce the supply voltage. Over the previous generations, shrinking the transistor geometry had been enabling the reduction of the supply voltage. However, at the 90 nm node, the fluctuation in the dopant distribution and the variation of the threshold voltage caused by the dopant fluctuation has become non-negligible, and it is no longer possible to lower the voltage just by shrinking the transistor.
A DDC transistor (Figure 1) contains layers of different dopant concentrations at the channel region. This structure helps reduce the fluctuation in the dopant distribution, which is a major cause of the threshold voltage variation, thus enables the lower supply voltage. Since the transistor is built on the conventional planar CMOS structure, it can be manufactured with the conventional semiconductor fabrication equipment. There is also another advantage of having the conventional CMOS structure, that circuit developers can reuse the existing design resources.
Fujitsu Semiconductor has developed CS250S, a combination of the 55 nm process in Mie Plant and the DDC, and successfully implemented the DDC technology into production for the first time in the world. In addition to reducing the dopant fluctuation by DDC, Adaptive Body Bias (ABB) control, which compensates the other process-induced variations by applying an optimum body bias for each die, CS250S has achieved the 50% lower active power compared with the conventional technology, while maintaining the same operation speed.
