Datasheet Texas Instruments ADC12D500RFIUT/NOPB
| Manufacturer | Texas Instruments |
| Series | ADC12D500RF |
| Part Number | ADC12D500RFIUT/NOPB |
12-Bit, Dual 500-MSPS or Single 1.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC) 292-BGA -40 to 85
Datasheets
ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC datasheet
PDF, 2.0 Mb, Revision: E, File published: Mar 25, 2013
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 292 |
| Package Type | NXA |
| Industry STD Term | BGA |
| JEDEC Code | S-PBGA-N |
| Package QTY | 40 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | ADC12D500RFIUT |
| Width (mm) | 27 |
| Length (mm) | 27 |
| Thickness (mm) | 2.38 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.4 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 2,1 |
| Analog Input BW | 2700 MHz |
| Architecture | Folding Interpolating |
| DNL(Max) | 0.4 +/-LSB |
| DNL(Typ) | 0.4 +/-LSB |
| ENOB | 9.7 Bits |
| INL(Max) | 2.5 +/-LSB |
| INL(Typ) | 2.5 +/-LSB |
| Input Buffer | Yes |
| Input Range | 0.8 Vp-p |
| Interface | Parallel LVDS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | BGA |
| Package Size: mm2:W x L | 292BGA: 729 mm2: 27 x 27(BGA) PKG |
| Power Consumption(Typ) | 2020 mW |
| Rating | Catalog |
| Reference Mode | Int |
| Resolution | 12 Bits |
| SFDR | 74.3 dB |
| SINAD | 60 dB |
| SNR | 60.4 dB |
| Sample Rate(Max) | 500,1000 MSPS |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: ADC12D800RFRB
12-Bit, Dual 800 MSPS or Single 1.6 GSPS A/D Converter Reference Board
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- From Sample Instant to Data Output: Understanding Latency in the GSPS ADCPDF, 392 Kb, File published: Dec 18, 2012
For many applications which use ultra high-speed ADCs, latency can be a critical performance specification. For example, if the ADC is used in any kind of feedback loop, then the absolute latency is an important factor. For a MIMO system such as a phased array radar, the relative difference and variability in latency becomes important. This application note covers latency in the GSPS ADC products, - Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of MitigatPDF, 720 Kb, File published: Dec 9, 2013
The SFDR performance of an ADC is limited by the largest spur in the spectrum from DC to Fs / 2. These spurs can either be reduced or avoided entirely for maximum SFDR performance, based on the application. This reference design explores the reason behind spurs in the 10-bit and 12-bit GSPS ADCfamily. The specific products covered are: ADC12D1800RF, ADC12D1600RF, ADC12D1000RF, ADC12D800RF, ADC12 - AN-2177 Using the LMH6554 as a ADC Driver (Rev. A)PDF, 1.7 Mb, Revision: A, File published: Apr 26, 2013
This application report discusses the use of the Texas Instruments LMH6554 as an ADC driver. - Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAsPDF, 943 Kb, File published: Aug 6, 2014
- AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G)PDF, 169 Kb, Revision: G, File published: Feb 3, 2017
Model Line
Series: ADC12D500RF (2)
- ADC12D500RFIUT ADC12D500RFIUT/NOPB
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
