Datasheet AD8018 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 5 V, Rail-to-Rail, High Output Current, xDSL Line Driver Amplifiers |
| Pages / Page | 20 / 10 — AD8018. Table I. Resistor Selection Guide. ERR. EOUT. Gain. RF (. RG (. … |
| Revision | A |
| File Format / Size | PDF / 377 Kb |
| Document Language | English |
AD8018. Table I. Resistor Selection Guide. ERR. EOUT. Gain. RF (. RG (. ADP3331. 330k. OUT. VOUT. 953k. 0.47. GND. 301k. OFF. POWER-DOWN FEATURES
Text Version of Document
AD8018 Table I. Resistor Selection Guide ERR EOUT Gain RF (
⍀
) RG (
⍀
) ADP3331 R3 330k
⍀ –1 681 681
OUT VOUT R1
+1 1 k ∞
V C2 IN IN 953k
⍀
0.47
F FB
+2 750 750
C1 0.47
F SD GND R2
+3 511 256
301k
⍀ +4 340 113
ON
+5 230 59
OFF
Figure 6. ADP3331 LDO
POWER-DOWN FEATURES
Two digitally programmable logic pins, PWDN1 and PWDN0,
METHOD FOR GENERATING A MIDSUPPLY VOLTAGE
are available on the TSSOP-14 package to select among three To operate an amplifier on a single voltage supply, a voltage different modes of operation, full power, standby and shutdown. midway between the supply and ground must be generated to The DGND pin is the logic ground reference. The logic thresh- properly bias the inputs and the outputs. old voltage is established 1 V above DGND. In a typical 5 V A voltage divider can be created with two equal value resistors single-supply application, the DGND pin is connected to analog (Figure 7). There is a trade-off between the power consumed by ground. If PWDN1, PWDN0, and DGND are left unconnected, the divider and the voltage drop across these resistors due to the the AD8018 will operate at full power. positive input bias currents. Selecting 2.5 kΩ for R1 and R2 will create a voltage divider that draws only 1 mA from a 5 V supply.
Table II. Power-Down Features and Truth Table
The voltage generated with this topology can vary due to the temperature coefficient (TC) of resistance. Resistors that are
Supply Output
closely matched and have a low TC will minimize variations in
PWDN0 PWDN1 State Current Impedance
the voltage reference due to temperature. One should also be High High Full Power 18 mA Low sure to use a decoupling capacitor (0.1 µF) at the node where Low High Standby 9 mA Low VREF is generated. High Low Standby 9 mA Low Low Low Disabled 300 µA High
5V R1 POWER SUPPLY AND DECOUPLING 2.5k
⍀
V
The AD8018 can be powered with a good quality (i.e., low-noise)
REF R2 0.1
F
supply anywhere in the range from 3.3 V to 8 V. However, in
2.5k
⍀ order to optimize the ADSL upstream drive capability to +13 dBm and maintain the best Spurious Free Dynamic Range (SFDR), Figure 7. Midsupply Reference the AD8018 circuit should be supplied with a well regulated 5 V supply. The 5 V supplied at the Universal Serial Bus (USB) port
DIFFERENTIAL TESTING
may be poorly regulated. Improving the quality of the 5 V supply The test circuit shown in TPC 13 is used for measuring the dif- will optimize the performance of the AD8018 in a Universal Serial ferential distortion of the AD8018. A single-ended test signal is Bus-supplied CPE ADSL modem. This can be accomplished applied to the inverting input of the AD8138 differential driver through the use of a step-up dc-to-dc converter or switching with the noninverting input grounded. Applying the differential power supply followed by a low dropout (LDO) regulator such output of the AD8138 through 100 Ω resistors serves to isolate as the ADP3331 (see Figure 6). Setting R1 to be 953 kΩ and the inputs of the AD8018 differential driver and provide a well- R2 to be 301 kΩ will result in a VOUT of 5 V. balanced low-distortion input signal. The differential load (RL) Careful attention must be paid to decoupling the power supply of the AD8018 can be set to the equivalent of the line imped- pins at the output of the dc-to-dc converter, the output of the ance reflected through a transformer. The AD9632 converts LDO regulator and the supply pins of the AD8018. High-quality the differential output voltage back to a single-ended signal. capacitors with low equivalent series resistance (ESR) such as The differential-to- single-ended converter using the AD9632 multilayer ceramic capacitors (MLCCs) should be used to mini- has an attenuation of –26 dB and is wired with precision resis- mize supply voltage ripple and power dissipation. A large, usually tors to optimize the balance of differential input signal. The tantalum, 10 µF to 47 µF capacitor located in proximity to the resulting smaller output signal can be easily measured using a AD8018 is required to provide good decoupling for lower fre- 50 Ω spectrum analyzer. quency signals. In addition, 0.1 µF MLCC decoupling capacitors should be located as close to each of the power supply pins as is physically possible, no more than 1/8 inch away. An additional large (4.7 µF to 10 µF) tantalum capacitor should be placed on the board near the supply terminals to supply current for fast, large- signal changes at the AD8018 outputs. REV. A –9–
⍀
) RG (
⍀
) ADP3331 R3 330k
⍀ –1 681 681
OUT VOUT R1
+1 1 k ∞
V C2 IN IN 953k
⍀
0.47
F FB
+2 750 750
C1 0.47
F SD GND R2
+3 511 256
301k
⍀ +4 340 113
ON
+5 230 59
OFF
Figure 6. ADP3331 LDO
POWER-DOWN FEATURES
Two digitally programmable logic pins, PWDN1 and PWDN0,
METHOD FOR GENERATING A MIDSUPPLY VOLTAGE
are available on the TSSOP-14 package to select among three To operate an amplifier on a single voltage supply, a voltage different modes of operation, full power, standby and shutdown. midway between the supply and ground must be generated to The DGND pin is the logic ground reference. The logic thresh- properly bias the inputs and the outputs. old voltage is established 1 V above DGND. In a typical 5 V A voltage divider can be created with two equal value resistors single-supply application, the DGND pin is connected to analog (Figure 7). There is a trade-off between the power consumed by ground. If PWDN1, PWDN0, and DGND are left unconnected, the divider and the voltage drop across these resistors due to the the AD8018 will operate at full power. positive input bias currents. Selecting 2.5 kΩ for R1 and R2 will create a voltage divider that draws only 1 mA from a 5 V supply.
Table II. Power-Down Features and Truth Table
The voltage generated with this topology can vary due to the temperature coefficient (TC) of resistance. Resistors that are
Supply Output
closely matched and have a low TC will minimize variations in
PWDN0 PWDN1 State Current Impedance
the voltage reference due to temperature. One should also be High High Full Power 18 mA Low sure to use a decoupling capacitor (0.1 µF) at the node where Low High Standby 9 mA Low VREF is generated. High Low Standby 9 mA Low Low Low Disabled 300 µA High
5V R1 POWER SUPPLY AND DECOUPLING 2.5k
⍀
V
The AD8018 can be powered with a good quality (i.e., low-noise)
REF R2 0.1
F
supply anywhere in the range from 3.3 V to 8 V. However, in
2.5k
⍀ order to optimize the ADSL upstream drive capability to +13 dBm and maintain the best Spurious Free Dynamic Range (SFDR), Figure 7. Midsupply Reference the AD8018 circuit should be supplied with a well regulated 5 V supply. The 5 V supplied at the Universal Serial Bus (USB) port
DIFFERENTIAL TESTING
may be poorly regulated. Improving the quality of the 5 V supply The test circuit shown in TPC 13 is used for measuring the dif- will optimize the performance of the AD8018 in a Universal Serial ferential distortion of the AD8018. A single-ended test signal is Bus-supplied CPE ADSL modem. This can be accomplished applied to the inverting input of the AD8138 differential driver through the use of a step-up dc-to-dc converter or switching with the noninverting input grounded. Applying the differential power supply followed by a low dropout (LDO) regulator such output of the AD8138 through 100 Ω resistors serves to isolate as the ADP3331 (see Figure 6). Setting R1 to be 953 kΩ and the inputs of the AD8018 differential driver and provide a well- R2 to be 301 kΩ will result in a VOUT of 5 V. balanced low-distortion input signal. The differential load (RL) Careful attention must be paid to decoupling the power supply of the AD8018 can be set to the equivalent of the line imped- pins at the output of the dc-to-dc converter, the output of the ance reflected through a transformer. The AD9632 converts LDO regulator and the supply pins of the AD8018. High-quality the differential output voltage back to a single-ended signal. capacitors with low equivalent series resistance (ESR) such as The differential-to- single-ended converter using the AD9632 multilayer ceramic capacitors (MLCCs) should be used to mini- has an attenuation of –26 dB and is wired with precision resis- mize supply voltage ripple and power dissipation. A large, usually tors to optimize the balance of differential input signal. The tantalum, 10 µF to 47 µF capacitor located in proximity to the resulting smaller output signal can be easily measured using a AD8018 is required to provide good decoupling for lower fre- 50 Ω spectrum analyzer. quency signals. In addition, 0.1 µF MLCC decoupling capacitors should be located as close to each of the power supply pins as is physically possible, no more than 1/8 inch away. An additional large (4.7 µF to 10 µF) tantalum capacitor should be placed on the board near the supply terminals to supply current for fast, large- signal changes at the AD8018 outputs. REV. A –9–
