Datasheet LTC1407, LTC1407A (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown |
| Pages / Page | 24 / 5 — TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over … |
| File Format / Size | PDF / 408 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating temperature
Model Line for this Datasheet
- LTC1407ACMSE#PBF LTC1407ACMSE#TRPBF LTC1407AHMSE#PBF LTC1407AHMSE#TRPBF LTC1407AIMSE#PBF LTC1407AIMSE#TRPBF LTC1407CMSE#PBF LTC1407CMSE#PBF LTC1407CMSE#TRPBF LTC1407CMSE#TRPBF LTC1407HMSE#PBF LTC1407HMSE#PBF LTC1407HMSE#TRPBF LTC1407HMSE#TRPBF LTC1407IMSE#PBF LTC1407IMSE#PBF LTC1407IMSE#TRPBF LTC1407IMSE#TRPBF
Text Version of Document
LTC1407/LTC1407A
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t7 32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns t9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
If less than 3ns is allowed, the output data will appear one may cause permanent damage to the device. Exposure to any Absolute clock cycle later. It is best for CONV to rise half a clock before SCK, when Maximum Rating condition for extended periods may affect device running the clock at rated speed. reliability and lifetime.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
Note 2:
All voltage values are with respect to ground GND. difference between the 2.2ns delay through the sample-and-hold and the
Note 3:
When these pins are taken below GND or above V 1.2ns CONV to Hold mode delay. DD, they will be clamped by internal diodes. This product can handle input currents greater
Note 12:
The rising edge of SCK is guaranteed to catch the data coming than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4:
Offset and range specifi cations apply for a single-ended CH0+ or CH1+
Note 13:
The time period for acquiring the input signal is started by the input with CH0– or CH1– grounded and using the internal 2.5V reference. 32nd rising clock and it is ended by the rising edge of CONV.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep defi ned as the deviation of a code from the straight line passing through mode with one or more cycles at SCK and a 10μF capacitive load. the actual endpoints of a transfer curve. The deviation is measured from
Note 15:
The full power bandwidth is the frequency where the output code the center of quantization band. swing drops by 3dB with a 2.5VP-P input sine wave.
Note 6:
Guaranteed by design, not subject to test.
Note 16:
Maximum clock period guarantees analog performance during
Note 7:
Recommended operating conditions. conversion. Output data can be read with an arbitrarily long clock period.
Note 8:
The analog input range is defi ned for the voltage difference
Note 17:
The LTC1407A is measured and specifi ed with 14-bit resolution between CH0+ and CH0– or CH1+ and CH1–. (1LSB = 152μV) and the LTC1407 is measured and specifi ed with 12-bit
Note 9:
The absolute voltage at CH0+, resolution (1LSB = 610μV). CH0–, CH1+ and CH1– must be within this range.
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407A) ENOBs and SINAD THD, 2nd and 3rd vs Input Sinewave Frequency vs Input Frequency SFDR vs Input Frequency
12.0 74 –44 104 –50 98 11.5 71 –56 THD 92 11.0 68 2nd –62 86 SINAD (dB) 10.5 65 –68 80 3rd 10.0 62 –74 74 –80 SFDR (dB) 68 ENOBs (BITS) 9.5 59 THD, 2nd, 3rd (dB) –86 62 9.0 56 –92 56 8.5 53 –98 50 8.0 50 –104 44 0.1 1 10 100 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 1407 G01 1407 G02 1407 G19 1407fb 5
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t7 32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns t9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
If less than 3ns is allowed, the output data will appear one may cause permanent damage to the device. Exposure to any Absolute clock cycle later. It is best for CONV to rise half a clock before SCK, when Maximum Rating condition for extended periods may affect device running the clock at rated speed. reliability and lifetime.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
Note 2:
All voltage values are with respect to ground GND. difference between the 2.2ns delay through the sample-and-hold and the
Note 3:
When these pins are taken below GND or above V 1.2ns CONV to Hold mode delay. DD, they will be clamped by internal diodes. This product can handle input currents greater
Note 12:
The rising edge of SCK is guaranteed to catch the data coming than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4:
Offset and range specifi cations apply for a single-ended CH0+ or CH1+
Note 13:
The time period for acquiring the input signal is started by the input with CH0– or CH1– grounded and using the internal 2.5V reference. 32nd rising clock and it is ended by the rising edge of CONV.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep defi ned as the deviation of a code from the straight line passing through mode with one or more cycles at SCK and a 10μF capacitive load. the actual endpoints of a transfer curve. The deviation is measured from
Note 15:
The full power bandwidth is the frequency where the output code the center of quantization band. swing drops by 3dB with a 2.5VP-P input sine wave.
Note 6:
Guaranteed by design, not subject to test.
Note 16:
Maximum clock period guarantees analog performance during
Note 7:
Recommended operating conditions. conversion. Output data can be read with an arbitrarily long clock period.
Note 8:
The analog input range is defi ned for the voltage difference
Note 17:
The LTC1407A is measured and specifi ed with 14-bit resolution between CH0+ and CH0– or CH1+ and CH1–. (1LSB = 152μV) and the LTC1407 is measured and specifi ed with 12-bit
Note 9:
The absolute voltage at CH0+, resolution (1LSB = 610μV). CH0–, CH1+ and CH1– must be within this range.
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407A) ENOBs and SINAD THD, 2nd and 3rd vs Input Sinewave Frequency vs Input Frequency SFDR vs Input Frequency
12.0 74 –44 104 –50 98 11.5 71 –56 THD 92 11.0 68 2nd –62 86 SINAD (dB) 10.5 65 –68 80 3rd 10.0 62 –74 74 –80 SFDR (dB) 68 ENOBs (BITS) 9.5 59 THD, 2nd, 3rd (dB) –86 62 9.0 56 –92 56 8.5 53 –98 50 8.0 50 –104 44 0.1 1 10 100 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 1407 G01 1407 G02 1407 G19 1407fb 5
