Datasheet LTC2265-12, LTC2264-12, LTC2263-12 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 12-Bit, 65Msps Low Power Dual ADCs |
| Pages / Page | 34 / 10 — TIMING DIAGRAMS. 1-Lane Output Mode, 14-Bit Serialization. 1-Lane Output … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
TIMING DIAGRAMS. 1-Lane Output Mode, 14-Bit Serialization. 1-Lane Output Mode, 12-Bit Serialization
Model Line for this Datasheet
- LTC2263CUJ-12#PBF LTC2263CUJ-12#PBF LTC2263CUJ-12#TRPBF LTC2263CUJ-12#TRPBF LTC2263IUJ-12#PBF LTC2263IUJ-12#PBF LTC2263IUJ-12#TRPBF LTC2263IUJ-12#TRPBF
Text Version of Document
LTC2265-12/ LTC2264-12/LTC2263-12
TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* D11 D10 D9 D8 OUT#A+ 226512 TD05 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUTA– D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 OUTA+ 226512 TD06 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUTB+, OUTB– ARE DISABLED 22654312fb 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* D11 D10 D9 D8 OUT#A+ 226512 TD05 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUTA– D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 OUTA+ 226512 TD06 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUTB+, OUTB– ARE DISABLED 22654312fb 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
