Datasheet AD7175-8 (Analog Devices) - 10

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Data Sheet AD7175-8 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS + – F F O3 N15 N14 N13 N12 N11 N10 N9 RE RE GP AI AI AI AI AI AI AI 40 39 38 37 36 35 34 33 32 31 AIN16 1 30 AIN8 AIN0/REF2– 2 29 AIN7 AIN1/REF2+ 3 28 AIN6 AIN2 4 AD7175-8 27 AIN5 AIN3 5 26 AIN4 TOP VIEW REFOUT 6 25 GPO2 REGCAPA 7 (Not to Scale) 24 GPIO1 AVSS 8 23 GPIO0 AVDD1 9 22 REGCAPD AVDD2 10 21 DGND 1 1 12 13 14 15 16 17 18 19 20 IO N K R C D SW L1 DI CS D TA LK RDY CL / PD X S SYN /C RRO UT E IOV L2 DO TA X NOTES 1. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR HEAT
005
DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB.
12911- Figure 4. Pin Configuration
Table 5. Pin Function Descriptions1 Pin No. Mnemonic Type2 Description
1 AIN16 AI Analog Input 16. This pin is selectable through the crosspoint multiplexer. 2 AIN0/REF2− AI Analog Input 0 (AIN0)/Reference 2, Negative Input (REF2−). An external reference can be applied between REF2+ and REF2−. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration registers. 3 AIN1/REF2+ AI Analog Input 1 (AIN0)/Reference 2, Positive Input (REF2+). An external reference can be applied between REF2+ and REF2−. REF2+ spans from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration registers. 4 AIN2 AI Analog Input 2. This pin is selectable through the crosspoint multiplexer. 5 AIN3 AI Analog Input 3. This pin is selectable through the crosspoint multiplexer. 6 REFOUT AO Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. 7 REGCAPA AO Analog Low Dropout (LDO) Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor. 8 AVSS P Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V. 9 AVDD1 P Analog Supply Voltage 1. This voltage is 5 V ± 10% with respect to AVSS. AVDD1 − AVSS can be a single 5 V supply or a ±2.5 V split supply. 10 AVDD2 P Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS. 11 PDSW AO Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register. 12 XTAL1 AI Input 1 for Crystal. 13 XTAL2/CLKIO AI/DI Input 2 for Crystal (XTAL2)/Clock Input or Output (CLKIO). See the CLOCKSEL bit settings in the ADCMODE register for more information. 14 DOUT/RDY DO Serial Data Output (DOUT)/Data Ready Output (RDY). This pin serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK fal ing edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. Rev. 0 | Page 9 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE