Datasheet AD7858, AD7858L (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 3 V to 5 V Single Supply, 200 kSPS, 8-Channel, 12-Bit, Serial Sampling ADC |
| Pages / Page | 32 / 10 — AD7858/AD7858L. CONTROL REGISTER. MSB. LSB. CONTROL REGISTER BIT FUNCTION … |
| Revision | B |
| File Format / Size | PDF / 309 Kb |
| Document Language | English |
AD7858/AD7858L. CONTROL REGISTER. MSB. LSB. CONTROL REGISTER BIT FUNCTION DESCRIPTION. Bit. Mnemonic. Comment
Model Line for this Datasheet
Text Version of Document
AD7858/AD7858L CONTROL REGISTER
The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de- scribed below. The power-up status of all bits is 0.
MSB
SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0 RDSLT1 RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL
LSB CONTROL REGISTER BIT FUNCTION DESCRIPTION Bit Mnemonic Comment
13 SGL/DIFF A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position configures the input channels in single-ended mode (see Table III). 12 CH2 These three bits are used to select the channel on which the conversion is performed. The channels can 11 CH1 be configured as eight single-ended channels or four pseudo-differential channels. The default selection 10 CH0 is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection). 9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various 8 PMGT0 Power-Down Modes (see Power-Down section for more details). 7 RDSLT1 Theses two bits determine which register is addressed for the read operations (see Table II). 6 RDSLT0 5 2/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1, Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to 1 in every write cycle. 4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration (see Calibration section.) 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions. 1 CALSLT0 With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per 0 STCAL formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration. With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the Calibration Registers for more details). –10– REV. B
The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de- scribed below. The power-up status of all bits is 0.
MSB
SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0 RDSLT1 RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL
LSB CONTROL REGISTER BIT FUNCTION DESCRIPTION Bit Mnemonic Comment
13 SGL/DIFF A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position configures the input channels in single-ended mode (see Table III). 12 CH2 These three bits are used to select the channel on which the conversion is performed. The channels can 11 CH1 be configured as eight single-ended channels or four pseudo-differential channels. The default selection 10 CH0 is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection). 9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various 8 PMGT0 Power-Down Modes (see Power-Down section for more details). 7 RDSLT1 Theses two bits determine which register is addressed for the read operations (see Table II). 6 RDSLT0 5 2/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1, Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to 1 in every write cycle. 4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration (see Calibration section.) 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions. 1 CALSLT0 With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per 0 STCAL formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration. With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the Calibration Registers for more details). –10– REV. B
