Datasheet LT1394 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 7ns, Low Power, Single Supply, Ground-Sensing Comparator |
| Pages / Page | 16 / 7 — APPLICATIONS INFORMATION. Common Mode Considerations. Input Bias Current. … |
| File Format / Size | PDF / 228 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Common Mode Considerations. Input Bias Current. LATCH Pin Dynamics. Measuring Response Time
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LT1394
U U W U APPLICATIONS INFORMATION Common Mode Considerations Input Bias Current
The LT1394 is specified for a common mode range of – 5V Input bias current is measured with the output held at to 3.5V on a ±5V supply or a common mode range of 0V 1.4V. As with any PNP differential input stage, the LT1394 to 3.5V on a single 5V supply. A more general consider- bias current flows out of the device. It will go to zero on an ation is that the common mode range is 0V below the input which is high and double on an input which is low. negative supply and 1.5V below the positive supply, inde- pendent of the actual supply voltage. The criterion for
LATCH Pin Dynamics
common mode limit is that the output still responds The LATCH pin is intended to retain input data (output correctly to a small differential input signal. latched) when the LATCH pin goes high. The pin will float When either input signal falls below the negative common to a high state when disconnected, so a flow-through mode limit, the internal PN diode formed with the sub- condition requires that the LATCH pin be grounded. The strate can turn on, resulting in significant current flow LATCH pin is designed to be driven with either a TTL or through the die. An external Schottky clamp diode CMOS output. It has no built-in hysteresis. between the input and the negative rail can speed up To guarantee data retention, the input signal must remain recovery from negative overdrive by preventing the sub- valid at least 2ns after the latch goes high (hold time), and strate diode from turning on. The zero-crossing detector must be valid at least – 0.4ns before the latch goes high in Figure 1 demonstrates the use of a fast clamp diode. (setup time). The negative setup time simply means that The zero-crossing detector terminates the transmission the data arriving 0.4ns after (rather than before) the latch line at its 50Ω characteristic impedance. Negative inputs signal is valid. When the latch signal goes low, new data should not fall below – 2V to keep the signal current within will appear at the output in approximately 6ns (latch the clamp diode’s maximum forward rating. Positive propagation delay). inputs should not exceed the device’s absolute maximum ratings or the power rating on the terminating resistor.
Measuring Response Time
Either input may go above the positive common mode To properly measure the response of the LT1394 requires limit without damaging the comparator. The upper voltage an input signal source with very fast rise times and limit is determined by an internal diode from each input to exceptionally clean settling characteristics. The last the positive supply. The input may go above the positive requirement comes about because the standard compara- supply as long as it does not go far enough above it to tor test calls for an input step size that is large compared conduct more than 10mA. Functionality will continue if the to the overdrive amplitude. Typical test conditions are remaining input stays within the allowed common mode 100mV step size with 5mV overdrive. This requires an range. There will, however, be an increase in propagation input signal that settles to within 1% (1mV) of final value delay as the input signal switches back into the common in only a few nanoseconds with no ringing or settling tail. mode range. Ordinary high speed pulse generators are not capable of generating such a signal, and in any case, no ordinary oscilloscope is capable of displaying the waveform to 5V RS check its fidelity. Some means must be used to inherently CABLE 50Ω VIN + generate a fast, clean edge with known final value. The Q RT 1N5712 LT1394 circuit shown in Figure 2 is the best electronic means of 50Ω – Q generating a fast, clean step to test comparators. It uses a very fast transistor in a common base configuration. The transistor is switched off with a fast edge from the genera- 1394 F01 tor and the collector voltage settles to exactly 0V in just a
Figure 1. Fast Zero-Crossing Detector
few nanoseconds. The most important feature of this 7
U U W U APPLICATIONS INFORMATION Common Mode Considerations Input Bias Current
The LT1394 is specified for a common mode range of – 5V Input bias current is measured with the output held at to 3.5V on a ±5V supply or a common mode range of 0V 1.4V. As with any PNP differential input stage, the LT1394 to 3.5V on a single 5V supply. A more general consider- bias current flows out of the device. It will go to zero on an ation is that the common mode range is 0V below the input which is high and double on an input which is low. negative supply and 1.5V below the positive supply, inde- pendent of the actual supply voltage. The criterion for
LATCH Pin Dynamics
common mode limit is that the output still responds The LATCH pin is intended to retain input data (output correctly to a small differential input signal. latched) when the LATCH pin goes high. The pin will float When either input signal falls below the negative common to a high state when disconnected, so a flow-through mode limit, the internal PN diode formed with the sub- condition requires that the LATCH pin be grounded. The strate can turn on, resulting in significant current flow LATCH pin is designed to be driven with either a TTL or through the die. An external Schottky clamp diode CMOS output. It has no built-in hysteresis. between the input and the negative rail can speed up To guarantee data retention, the input signal must remain recovery from negative overdrive by preventing the sub- valid at least 2ns after the latch goes high (hold time), and strate diode from turning on. The zero-crossing detector must be valid at least – 0.4ns before the latch goes high in Figure 1 demonstrates the use of a fast clamp diode. (setup time). The negative setup time simply means that The zero-crossing detector terminates the transmission the data arriving 0.4ns after (rather than before) the latch line at its 50Ω characteristic impedance. Negative inputs signal is valid. When the latch signal goes low, new data should not fall below – 2V to keep the signal current within will appear at the output in approximately 6ns (latch the clamp diode’s maximum forward rating. Positive propagation delay). inputs should not exceed the device’s absolute maximum ratings or the power rating on the terminating resistor.
Measuring Response Time
Either input may go above the positive common mode To properly measure the response of the LT1394 requires limit without damaging the comparator. The upper voltage an input signal source with very fast rise times and limit is determined by an internal diode from each input to exceptionally clean settling characteristics. The last the positive supply. The input may go above the positive requirement comes about because the standard compara- supply as long as it does not go far enough above it to tor test calls for an input step size that is large compared conduct more than 10mA. Functionality will continue if the to the overdrive amplitude. Typical test conditions are remaining input stays within the allowed common mode 100mV step size with 5mV overdrive. This requires an range. There will, however, be an increase in propagation input signal that settles to within 1% (1mV) of final value delay as the input signal switches back into the common in only a few nanoseconds with no ringing or settling tail. mode range. Ordinary high speed pulse generators are not capable of generating such a signal, and in any case, no ordinary oscilloscope is capable of displaying the waveform to 5V RS check its fidelity. Some means must be used to inherently CABLE 50Ω VIN + generate a fast, clean edge with known final value. The Q RT 1N5712 LT1394 circuit shown in Figure 2 is the best electronic means of 50Ω – Q generating a fast, clean step to test comparators. It uses a very fast transistor in a common base configuration. The transistor is switched off with a fast edge from the genera- 1394 F01 tor and the collector voltage settles to exactly 0V in just a
Figure 1. Fast Zero-Crossing Detector
few nanoseconds. The most important feature of this 7
