Datasheet LT1715 (Analog Devices) - 10

LT1715
APPLICATIONS INFORMATION
When both input signals are above the positive common
High Speed Design Considerations
mode limit, the input stage will get debiased and the output Application of high speed comparators is often plagued by polarity will be random. However, the internal hysteresis oscillations. The LT1715 has 4mV of internal hysteresis, will hold the output to a valid logic level. When at least one which will prevent oscillations as long as parasitic output of the inputs returns to within the common mode limits, to input feedback is kept below 4mV. However, with the recovery from this state will take as long as 1μs. 2V/ns slew rate of the LT1715 outputs, a 4mV step can The propagation delay does not increase signifi cantly when be created at a 100Ω input source with only 0.02pF of driven with large differential voltages, but with low levels output to input coupling. The LT1715’s pinout has been of overdrive, an apparent increase may be seen with large arranged to minimize problems by placing the sensitive source resistances due to an RC delay caused by the 2pF inputs away from the outputs, shielded by the power rails. typical input capacitance. The input and output traces of the circuit board should also be separated, and the requisite level of isolation is
Input Protection
readily achieved if a topside ground plane runs between The input stage is protected against damage from large the output and the inputs. For multilayer boards where the differential signals, up to and beyond a differential voltage ground plane is internal, a topside ground or supply trace equal to the supply voltage, limited only by the absolute should be run between the inputs and the output. maximum currents noted. External input protection cir- The ground pin of the LT1715 can disturb the ground plane cuitry is only needed if currents would otherwise exceed potential while toggling due to the extremely fast on and these absolute maximums. The internal catch diodes can off times of the output stage. Therefore, using a ground conduct current up to these rated maximums without for input termination or fi ltering that is separate from the latchup, even when the supply voltages are at the absolute LT1715 Pin 6 ground can be highly benefi cial. For example, maximum ratings. a ground plane tied to Pin 6 and directly adjacent to a 1" The LT1715 input stage has general purpose internal ESD long input trace can capacitively couple 4mV of disturbance protection for the human body model. For use as a line into the input. In this scenario, cutting the ground plane receiver, additional external protection may be required. between the GND pin and the inputs will cut the capacitance As with most integrated circuits, the level of immunity to and the disturbance down substantially. ESD is much greater when residing on a printed circuit Figure 2 shows a typical topside layout of the LT1715 board where the power supply decoupling capacitance will on such a multilayer board. Shown is the topside metal limit the voltage rise caused by an ESD pulse. etch including traces, pin escape vias, and the land pads for an MS10 LT1715 and its adjacent X7R 10nF bypass
Input Bias Current
capacitors in the 0805 case. Input bias current is measured with both inputs held at 1V. As with any PNP differential input stage, the LT1715 bias current fl ows out of the device. It will go to zero on the higher of the two inputs and double on the lower of the two inputs. With more than two diode drops of differential input voltage, the LT1715’s input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias 1715 F02 current into the higher of the two input pins, of 4μA or less. See the Typical Performance curve “Input Current vs Differential Input Voltage.”
Figure 2. Typical Topside Metal for Multilayer PCB Layouts
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