Datasheet MCP6041, MCP6042, MCP6043, MCP6044 (Microchip) - 2
| Manufacturer | Microchip |
| Description | Оperational amplifier (op amp) has a gain bandwidth product of 14 kHz with a low typical operating current of 600 nA and an offset voltage that is less than 3 mV |
| Pages / Page | 40 / 2 — MCP6041/2/3/4. 1.0. ELECTRICAL. † Notice:. CHARACTERISTICS. Absolute … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
MCP6041/2/3/4. 1.0. ELECTRICAL. † Notice:. CHARACTERISTICS. Absolute Maximum Ratings †. Section 4.1 “Rail-to-Rail Input”
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MCP6041/2/3/4 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD – VSS ..7.0V periods may affect device reliability. Current at Input Pins ...±2 mA
††
See
Section 4.1 “Rail-to-Rail Input”
Analog Inputs (VIN+, VIN–) ... VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs .. VSS – 0.3V to VDD + 0.3V Difference Input voltage .. |VDD – VSS| Output Short Circuit Current ..continuous Current at Output and Supply Pins ..±30 mA Storage Temperature.. –65°C to +150°C Junction Temperature.. +150°C ESD protection on all pins (HBM; MM) 4 kV; 200V
DC ELECTRICAL CHARACTERISTICS Electrical Characteristics:
Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, V OUT VDD/2, VL = VDD/2, and RL = 1 Mto VL (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage VOS -3 — +3 mV VCM = VSS Drift with Temperature VOS/TA — ±2 — µV/°C VCM = VSS, TA= -40°C to +85°C VOS/TA — ±15 — µV/°C VCM = VSS, TA= +85°C to +125°C Power Supply Rejection PSRR 70 85 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB — 1 — pA Industrial Temperature IB — 20 100 pA TA = +85° Extended Temperature IB — 1200 5000 pA TA = +125° Input Offset Current IOS — 1 — pA Common Mode Input Impedance ZCM — 1013||6 — ||pF Differential Input Impedance ZDIFF — 1013||6 — ||pF
Common Mode
Common-Mode Input Range V CMR VSS 0.3 — VDD+0.3 V Common-Mode Rejection Ratio CMRR 62 80 — dB VDD = 5V, VCM = -0.3V to 5.3V CMRR 60 75 — dB VDD = 5V, VCM = 2.5V to 5.3V CMRR 60 80 — dB VDD = 5V, VCM = -0.3V to 2.5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 95 115 — dB RL = 50 k to VL, V OUT = 0.1V to VDD 0.1V
Output
Maximum Output Voltage Swing V OL, VOH VSS + 10 — VDD 10 mV RL = 50 k to VL, 0.5V input overdrive Linear Region Output Voltage Swing V OVR VSS + 100 — VDD 100 mV RL = 50 k to VL, A OL 95 dB Output Short Circuit Current ISC — 2 — mA VDD = 1.4V ISC — 20 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.4 — 6.0 V
(Note 1)
Quiescent Current per Amplifier IQ 0.3 0.6 1.0 µA IO = 0
Note 1:
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.4V and/or 5.5V. DS21669D-page 2 2001-2013 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
MCP6041/2/3/4 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD – VSS ..7.0V periods may affect device reliability. Current at Input Pins ...±2 mA
††
See
Section 4.1 “Rail-to-Rail Input”
Analog Inputs (VIN+, VIN–) ... VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs .. VSS – 0.3V to VDD + 0.3V Difference Input voltage .. |VDD – VSS| Output Short Circuit Current ..continuous Current at Output and Supply Pins ..±30 mA Storage Temperature.. –65°C to +150°C Junction Temperature.. +150°C ESD protection on all pins (HBM; MM) 4 kV; 200V
DC ELECTRICAL CHARACTERISTICS Electrical Characteristics:
Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, V OUT VDD/2, VL = VDD/2, and RL = 1 Mto VL (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage VOS -3 — +3 mV VCM = VSS Drift with Temperature VOS/TA — ±2 — µV/°C VCM = VSS, TA= -40°C to +85°C VOS/TA — ±15 — µV/°C VCM = VSS, TA= +85°C to +125°C Power Supply Rejection PSRR 70 85 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB — 1 — pA Industrial Temperature IB — 20 100 pA TA = +85° Extended Temperature IB — 1200 5000 pA TA = +125° Input Offset Current IOS — 1 — pA Common Mode Input Impedance ZCM — 1013||6 — ||pF Differential Input Impedance ZDIFF — 1013||6 — ||pF
Common Mode
Common-Mode Input Range V CMR VSS 0.3 — VDD+0.3 V Common-Mode Rejection Ratio CMRR 62 80 — dB VDD = 5V, VCM = -0.3V to 5.3V CMRR 60 75 — dB VDD = 5V, VCM = 2.5V to 5.3V CMRR 60 80 — dB VDD = 5V, VCM = -0.3V to 2.5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 95 115 — dB RL = 50 k to VL, V OUT = 0.1V to VDD 0.1V
Output
Maximum Output Voltage Swing V OL, VOH VSS + 10 — VDD 10 mV RL = 50 k to VL, 0.5V input overdrive Linear Region Output Voltage Swing V OVR VSS + 100 — VDD 100 mV RL = 50 k to VL, A OL 95 dB Output Short Circuit Current ISC — 2 — mA VDD = 1.4V ISC — 20 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.4 — 6.0 V
(Note 1)
Quiescent Current per Amplifier IQ 0.3 0.6 1.0 µA IO = 0
Note 1:
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.4V and/or 5.5V. DS21669D-page 2 2001-2013 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6043 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +25°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6041/2/3/4 family shows no phase reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6042 and MCP6044 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6043 only). FIGURE 2-33: Input Current vs. Input Voltage (below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6043 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.5 MCP6043 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High-Side Battery Current Sensor. FIGURE 4-8: Two Op Amp Instrumentation Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
