Datasheet LTC1278 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 12-Bit, 500ksps Sampling A/D Converter with Shutdown |
| Pages / Page | 16 / 8 — TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output … |
| File Format / Size | PDF / 290 Kb |
| Document Language | English |
TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay. W U. TI I G DIAGRA S. CS to RD Setup Timing
Model Line for this Datasheet
- LTC1278-4CN#PBF LTC1278-4CSW#PBF LTC1278-4CSW#TRPBF LTC1278-4IN#PBF LTC1278-4ISW#PBF LTC1278-4ISW#TRPBF LTC1278-5CSW#PBF LTC1278-5CSW#TRPBF LTC1278-5ISW#PBF LTC1278-5ISW#TRPBF
Text Version of Document
LTC1278
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t8) B) HIGH-Z TO VOL (t8) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1278 • TA08 LTC1278 TA08
W U W TI I G DIAGRA S CS to RD Setup Timing CS to CONVST Setup Timing SHDN to CONVST Wake-Up Timing
CS CS SHDN t1 t2 t3 RD CONVST CONVST LTC1278 • TC01 LTC1278 • TC02 LTC1278 • TC03
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
SAMPLE The LTC1278 uses a successive approximation algorithm C SI SAMPLE SAMPLE and an internal sample-and-hold circuit to convert an A – IN analog signal to a 12-bit parallel output. The ADC is HOLD complete with a precision reference and an internal clock. + CDAC COMPARATOR The control logic provides easy interface to microproces- DAC sors and DSPs. (Please refer to the Digital Interface VDAC S section for the data format.) A R Conversion start is controlled by the CS and CONVST inputs. At the start of conversion the successive approxi- 12-BIT LATCH mation register (SAR) is reset. Once a conversion cycle LTC1278 F1 has begun it cannot be restarted.
Figure 1. AIN Input
During conversion, the internal 12-bit capacitive DAC offset is nulled by the feedback switch. In this acquire output is sequenced by the SAR from the most significant phase, a minimum delay of 200ns will provide enough bit (MSB) to the least significant bit (LSB). Referring to time for the sample-and-hold capacitor to acquire the Figure 1, the AIN input connects to the sample-and-hold analog signal. During the convert phase, the comparator capacitor during the acquire phase, and the comparator feedback switch opens, putting the comparator into the 8
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t8) B) HIGH-Z TO VOL (t8) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1278 • TA08 LTC1278 TA08
W U W TI I G DIAGRA S CS to RD Setup Timing CS to CONVST Setup Timing SHDN to CONVST Wake-Up Timing
CS CS SHDN t1 t2 t3 RD CONVST CONVST LTC1278 • TC01 LTC1278 • TC02 LTC1278 • TC03
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
SAMPLE The LTC1278 uses a successive approximation algorithm C SI SAMPLE SAMPLE and an internal sample-and-hold circuit to convert an A – IN analog signal to a 12-bit parallel output. The ADC is HOLD complete with a precision reference and an internal clock. + CDAC COMPARATOR The control logic provides easy interface to microproces- DAC sors and DSPs. (Please refer to the Digital Interface VDAC S section for the data format.) A R Conversion start is controlled by the CS and CONVST inputs. At the start of conversion the successive approxi- 12-BIT LATCH mation register (SAR) is reset. Once a conversion cycle LTC1278 F1 has begun it cannot be restarted.
Figure 1. AIN Input
During conversion, the internal 12-bit capacitive DAC offset is nulled by the feedback switch. In this acquire output is sequenced by the SAR from the most significant phase, a minimum delay of 200ns will provide enough bit (MSB) to the least significant bit (LSB). Referring to time for the sample-and-hold capacitor to acquire the Figure 1, the AIN input connects to the sample-and-hold analog signal. During the convert phase, the comparator capacitor during the acquire phase, and the comparator feedback switch opens, putting the comparator into the 8
