Datasheet LTC1289 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 3 Volt Single Chip 12-Bit Data Acquisition System |
| Pages / Page | 28 / 9 — APPLICATI. S I FOR ATIO. DIGITAL CONSIDERATIONS. Serial Interface. Input … |
| File Format / Size | PDF / 685 Kb |
| Document Language | English |
APPLICATI. S I FOR ATIO. DIGITAL CONSIDERATIONS. Serial Interface. Input Data Word. Operating Sequence
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LTC1289
O U U W U APPLICATI S I FOR ATIO
The LTC1289 is a data acquisition component which previous conversion is output on the DOUT line. At the end contains the following functional blocks: of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is 1. 12-bit successive approximation capacitive A/D complete and the results will be available on the next data converter transfer cycle. As shown below, the result of a conversion 2. Analog multiplexer (MUX) is delayed by one CS cycle from the input word requesting 3. Sample-and-hold (S/H) it. 4. Synchronous, full duplex serial interface DIN DIN WORD 1 D D IN WORD 2 IN WORD 3 5. Control and timing logic DOUT DOUT WORD 0 D D OUT WORD 1 OUT WORD 2 t t
DIGITAL CONSIDERATIONS
DATA CONV DATA CONV A/D A/D TRANSFER TRANSFER CONVERSION CONVERSION LTC1289 AI01
Serial Interface
The LTC1289 communicates with microprocessors and
Input Data Word
other external circuitry via a synchronous, full duplex, four The LTC1289 8-bit data word is clocked into the DIN input wire serial interface (see Operating Sequence). The shift on the first eight rising SCLK edges after chip select is clock (SCLK) synchronizes the data transfer with each bit recognized. Further inputs on the DIN pin are then ignored being transmitted on the falling SCLK edge and captured until the next CS cycle. The eight bits of the input word are on the rising SCLK edge in both transmitting and receiving defined as follows: systems. The data is transmitted and received simulta- neously (full duplex). UNIPOLAR/ WORD BIPOLAR LENGTH Data transfer is initiated by a falling chip select (CS) signal. SGL/ ODD/ SELECT SELECT After the falling CS is recognized, an 8-bit input word is UNI MSBF WL1 WL0 DIFF SIGN 1 0 shifted into the DIN input which configures the LTC1289 for the next conversion. Simultaneously, the result of the MUX ADDRESS MSB-FIRST/ LSB-FIRST LTC1289 AI02
Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
tCYC 1 2 3 4 5 6 7 8 9 10 11 12 SCLK DON'T CARE t t SMPL CONV CS D DON'T CARE IN D B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 OUT SHIFT CONFIGURATION (SB) SHIFT A/D RESULT OUT AND WORD IN NEW CONFIGURATION WORD IN LTC1289 AI03 1289fb 9
O U U W U APPLICATI S I FOR ATIO
The LTC1289 is a data acquisition component which previous conversion is output on the DOUT line. At the end contains the following functional blocks: of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is 1. 12-bit successive approximation capacitive A/D complete and the results will be available on the next data converter transfer cycle. As shown below, the result of a conversion 2. Analog multiplexer (MUX) is delayed by one CS cycle from the input word requesting 3. Sample-and-hold (S/H) it. 4. Synchronous, full duplex serial interface DIN DIN WORD 1 D D IN WORD 2 IN WORD 3 5. Control and timing logic DOUT DOUT WORD 0 D D OUT WORD 1 OUT WORD 2 t t
DIGITAL CONSIDERATIONS
DATA CONV DATA CONV A/D A/D TRANSFER TRANSFER CONVERSION CONVERSION LTC1289 AI01
Serial Interface
The LTC1289 communicates with microprocessors and
Input Data Word
other external circuitry via a synchronous, full duplex, four The LTC1289 8-bit data word is clocked into the DIN input wire serial interface (see Operating Sequence). The shift on the first eight rising SCLK edges after chip select is clock (SCLK) synchronizes the data transfer with each bit recognized. Further inputs on the DIN pin are then ignored being transmitted on the falling SCLK edge and captured until the next CS cycle. The eight bits of the input word are on the rising SCLK edge in both transmitting and receiving defined as follows: systems. The data is transmitted and received simulta- neously (full duplex). UNIPOLAR/ WORD BIPOLAR LENGTH Data transfer is initiated by a falling chip select (CS) signal. SGL/ ODD/ SELECT SELECT After the falling CS is recognized, an 8-bit input word is UNI MSBF WL1 WL0 DIFF SIGN 1 0 shifted into the DIN input which configures the LTC1289 for the next conversion. Simultaneously, the result of the MUX ADDRESS MSB-FIRST/ LSB-FIRST LTC1289 AI02
Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
tCYC 1 2 3 4 5 6 7 8 9 10 11 12 SCLK DON'T CARE t t SMPL CONV CS D DON'T CARE IN D B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 OUT SHIFT CONFIGURATION (SB) SHIFT A/D RESULT OUT AND WORD IN NEW CONFIGURATION WORD IN LTC1289 AI03 1289fb 9
