Datasheet LTC2289 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual 10-Bit, 80Msps Low Noise 3V ADC |
| Pages / Page | 24 / 10 — TI I G DIAGRA S. Dual Digital Output Bus Timing. (Only One Channel is … |
| File Format / Size | PDF / 677 Kb |
| Document Language | English |
TI I G DIAGRA S. Dual Digital Output Bus Timing. (Only One Channel is Shown). Multiplexed Digital Output Bus Timing
Model Line for this Datasheet
Text Version of Document
LTC2289
W U W TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown)
tAP N + 2 N + 4 ANALOG N INPUT N + 1 N + 3 N + 5 tH tL CLK tD D0-D9, OF N – 5 N – 4 N – 3 N – 2 N – 1 N 2289 TD01
Multiplexed Digital Output Bus Timing
tAPA A + 2 A + 4 ANALOG A INPUT A A + 1 A + 3 tAPB B + 2 B + 4 ANALOG B INPUT B B + 1 B + 3 tH tL CLKA = CLKB = MUX D0A-D9A, OFA A – 5 B – 5 A – 4 B – 4 A – 3 B – 3 A – 2 B – 2 A – 1 tD tMD D0B-D9B, OFB B – 5 A – 5 B – 4 A – 4 B – 3 A – 3 B – 2 A – 2 B – 1 2289 TD02 2289fa 10
W U W TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown)
tAP N + 2 N + 4 ANALOG N INPUT N + 1 N + 3 N + 5 tH tL CLK tD D0-D9, OF N – 5 N – 4 N – 3 N – 2 N – 1 N 2289 TD01
Multiplexed Digital Output Bus Timing
tAPA A + 2 A + 4 ANALOG A INPUT A A + 1 A + 3 tAPB B + 2 B + 4 ANALOG B INPUT B B + 1 B + 3 tH tL CLKA = CLKB = MUX D0A-D9A, OFA A – 5 B – 5 A – 4 B – 4 A – 3 B – 3 A – 2 B – 2 A – 1 tD tMD D0B-D9B, OFB B – 5 A – 5 B – 4 A – 4 B – 3 A – 3 B – 2 A – 2 B – 1 2289 TD02 2289fa 10
