Datasheet LTC2453 (Analog Devices) - 7

LTC2453
APPLICATIONS INFORMATION CONVERTER OPERATION
edges of SCL, allowing the user to reliably latch data on the rising edge of SCL. A new conversion is initiated by
Converter Operation Cycle
a stop condition following a valid read operation, or by The LTC2453 is a low-power, fully differential, delta-sigma the conclusion of a complete read cycle (all 16 bits read analog-to-digital converter with an I2C interface. Its oper- out of the device). ation, as shown in Figure 1, is composed of three suc-
Power-Up Sequence
cessive states: CONVERSION, SLEEP and DATA OUTPUT. When the power supply voltage (VCC) applied to the con- Initially, at power up, the LTC2453 performs a conversion. verter is below approximately 2.1V, the ADC performs a Once the conversion is complete, the device enters the power-on reset. This feature guarantees the integrity of sleep state. While in this sleep state, power consumption is the conversion result. reduced by several orders of magnitude. The part remains in the sleep state as long as it is not addressed for a read When VCC rises above this threshold, the converter gener- operation. The conversion result is held indefinitely in a ates an internal power-on reset (POR) signal for approxi- static shift register while the part is in the sleep state. mately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2453 starts a conversion cycle and follows the succession of states described in POWER-ON RESET Figure 1. The first conversion result following POR is ac- CONVERSION curate within the specifications of the device if the power supply voltage VCC is restored within the operating range SLEEP (2.7V to 5.5V) before the end of the POR time interval.
Ease of Use
READ NO ACKNOWLEDGE The LTC2453 data output has no latency, filter settling delay or redundant results associated with the conversion YES cycle. There is a one-to-one correspondence between the DATA OUTPUT conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. STOP The LTC2453 performs offset calibrations every conver- NO OR READ sion. This calibration is transparent to the user and has 16-BITS no effect upon the cyclic operation described previ- YES ously. The advantage of continuous calibration is extreme 2453 F01 stability of the ADC performance with respect to time and
Figure 1. LTC2453 State Diagram
temperature. The LTC2453 includes a proprietary input sampling scheme The device will not acknowledge an external request during that reduces the average input current by several orders the conversion state. After a conversion is finished, the of magnitude when compared to traditional delta-sigma device is ready to accept a read request. The LTC2453’s architectures. This allows external filter networks to in- address is hard-wired at 0010100. Once the LTC2453 is terface directly to the LTC2453. Since the average input addressed for a read operation, the device begins output- sampling current is 50nA, an external RC lowpass filter ting the conversion result under the control of the serial using a 1kΩ and 0.1µF results in <1LSB additional error. clock (SCL). There is no latency in the conversion result. Additionally, there is negligible leakage current between The data output is 16 bits long and contains a 15-bit plus IN+ and IN–. sign conversion result. Data is updated on the falling 2453fc 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs And References Power Requirements I2C Inputs And Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Application Package Description Revision History Related Parts