Datasheet AD7616-P (Analog Devices) - 7

link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8
AD7616-P Data Sheet TIMING SPECIFICATIONS
Note that throughout the timing specifications, multifunction pins, such as WR/ BURST, are referred to either by the entire pin name or by a single function of the pin, for example, WR, when only that function is relevant.
Universal Timing Specifications
VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, VREF = 2.5 V external reference/internal reference, TA = −40°C to +125°C, unless otherwise noted. Interface timing tested using a load capacitance of 30 pF.
Table 2. Parameter1 Min Typ Max Unit Description
t 1 µs Minimum time between consecutive CONVST rising edges (excluding burst and CYCLE oversampling modes) t 50 ns CONVST low pulse width CONV_LOW t 50 ns CONVST high pulse width CONV_HIGH t 34 ns CONVST high to BUSY high (manual mode) BUSY_DELAY t 20 ns BUSY fal ing edge to CS fal ing edge setup time CS_SETUP t 50 ns Channel select setup time in hardware mode for CHSELx CH_SETUP t 20 ns Channel select hold time in hardware mode for CHSELx CH_HOLD t 475 530 ns Conversion time for the selected channel pair CONV t 470 ns Acquisition time for the selected channel pair ACQ t 50 ns QUIET CS rising edge to next CONVST rising edge t See Figure 3 RESET_LOW Partial Reset 40 500 ns Partial RESET low pulse width Full Reset 1.2 µs Full RESET low pulse width t See Figure 3 DEVICE_SETUP Partial Reset 120 ns Time between partial RESET high and CONVST rising edge Full Reset 15 ms Time between full RESET high and CONVST rising edge t See Figure 3 WRITE Partial Reset 50 ns Time between partial RESET high and CS for write operation Full Reset 240 µs Time between full RESET high and CS for write operation t 1 ms Time between stable V /V and release of RESET (see Figure 3) RESET_WAIT CC DRIVE t Time prior to release of RESET that queried hardware inputs must be stable for (see Figure 3) RESET_SETUP Partial Reset 10 ns Full Reset 0.05 ms t Time after release of RESET that latched hardware inputs must be stable for (see Figure 3) RESET_HOLD Partial Reset 10 ns Full Reset 0.24 ms 1 Not production tested. Sample tested during initial release to ensure compliance.
tCYCLE t t CONV_LOW CONV_HIGH t t QUIET BUSY_DELAY CONVST BUSY t t CONV ACQ tCS_SETUP CS tCH_SETUP tCH_HOLD
002
HARDWARE CHSEL0 TO MODE ONLY CHSEL2 CHX CHY
15695- Figure 2. Universal Timing Diagram Across All Interfaces Rev. 0 | Page 6 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Universal Timing Specifications Parallel Interface Timing Specifications ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Channel Selection Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE SHUTDOWN MODE DIGITAL FILTER APPLICATIONS INFORMATION FUNCTIONALITY OVERVIEW POWER SUPPLIES TYPICAL CONNECTIONS DEVICE CONFIGURATION OPERATIONAL MODE INTERNAL/EXTERNAL REFERENCE HARDWARE MODE SOFTWARE MODE RESET FUNCTIONALITY PIN FUNCTION OVERVIEW DIGITAL INTERFACE CHANNEL SELECTION Hardware Mode Software Mode PARALLEL INTERFACE Reading Conversion Results Writing Register Data Reading Register Data SEQUENCER HARDWARE MODE SEQUENCER SOFTWARE MODE SEQUENCER BURST SEQUENCER Hardware Mode Burst Software Mode Burst DIAGNOSTICS DIAGNOSTIC CHANNELS INTERFACE SELF TEST CRC REGISTER SUMMARY ADDRESSING REGISTERS CONFIGURATION REGISTER CHANNEL REGISTER INPUT RANGE REGISTERS Input Range Register A1 Input Range Register A2 Input Range Register B1 Input Range Register B2 SEQUENCER STACK REGISTERS Sequencer Stack Register 0 to Sequencer Stack Register 7 Sequencer Stack Register 8 to Sequencer Stack Register 31 STATUS REGISTER OUTLINE DIMENSIONS ORDERING GUIDE