Datasheet AD9694 (Analog Devices)

14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter Data Sheet AD9694 FEATURES Amplitude detect bits for efficient AGC implementation JESD204B (Subclass 1) coded serial digital outputs 4 integrated wideband digital processors Lane rates up to 15 Gbps 48-bit NCO, up to 4 cascaded half-band filters 1.66 W total power at 500 MSPS Differential clock input 415 mW per analog-to-digital converter (ADC) channel Integer clock divide by 1, 2, 4, or 8 SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range) On-chip temperature diode SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range) Flexible JESD204B lane configurations Noise density = −151.5 dBFS/Hz (1.80 V p-p input range) APPLICATIONS 0.975 V, 1.8 V, and 2.5 V dc supply operation Communications No missing codes Diversity multiband, multimode digital receivers Internal ADC voltage reference 3G/4G, W-CDMA, GSM, LTE, LTE-A Analog input buffer General-purpose software radios On-chip dithering to improve small signal linearity Ultrawideband satellite receivers Flexible differential input range Instrumentation 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal) Radars 1.4 GHz analog input full power bandwidth Signals intelligence (SIGINT) FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD1_SR AVDD2 AVDD3 DVDD DRVDD DRVDD2 SPIVDD (0.975V) (0.975V) (1.8V) (2.5V) (0.975V) (0.975V) (1.8V) (1.8V) BUFFER 14 DIGITAL DOWN VIN+A ADC CONVERTER CORE (DDC) VIN–A 2 VCM_AB JESD204B SERDOUT0AB± Tx FD_A HIGH-SPEED FAST SIGNAL OUTPUTS SERIALIZER SERDOUT1AB± DETECT MONITOR FD_B BUFFER 14 DIGITAL DOWN VIN+B ADC CONVERTER CORE (DDC) VIN–B SIGNAL MONITOR AND FAST DETECT SYSREF± CLOCK JESD204B CLK+ GENERATION SUBCLASS 1 SYNCINB±AB CONTROL SYNCINB±CD CLK– ÷2 ÷4 ÷8 BUFFER 14 DIGITAL DOWN VIN+C ADC CONVERTER CORE (DDC) VIN–C 2 VCM_CD JESD204B Tx SERDOUT0CD± FD_C HIGH-SPEED FAST SIGNAL OUTPUTS SERDOUT1CD± SERIALIZER DETECT MONITOR FD_D BUFFER VIN+D 14 DIGITAL DOWN ADC CONVERTER CORE (DDC) VIN–D SPI CONTROL PDWN/STBY AD9694
001
AGND DRGND SDIO SCLK CSB
14808- Figure 1.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Dither Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C, AND FD_D) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO AND MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS OVERVIEW HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE SETTING UP THE AD9694 DIGITAL INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) JESD204B Tx CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) LATENCY END-TO-END TOTAL LATENCY MULTICHIP SYNCHRONIZATION SYSREF± SET UP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels ADC Pair Addressing Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE SUMMARY MEMORY MAP REGISTER TABLE—DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND PIN 67) OUTLINE DIMENSIONS ORDERING GUIDE