Datasheet AD9694 (Analog Devices) - 4

Data Sheet AD9694 GENERAL DESCRIPTION
Users can configure each pair of intermediate frequency (IF) The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital receiver outputs onto either one or two lanes of Subclass 1 converter (ADC). The device has an on-chip buffer and a JESD204B-based high speed serialized outputs, depending on sample-and-hold circuit designed for low power, small size, and the decimation ratio and the acceptable lane rate of the receiving ease of use. This device is designed for sampling wide bandwidth logic device. Multiple device synchronization is supported through analog signals of up to 1.4 GHz. The AD9694 is optimized for the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins. wide input bandwidth, high sampling rate, excellent linearity, The AD9694 has flexible power-down options that al ow significant and low power in a small package. power savings when desired. All of these features can be pro- The quad ADC cores feature a multistage, differential pipelined grammed using the 1.8 V capable, 3-wire SPI. architecture with integrated output error correction logic. Each The AD9694 is available in a Pb-free, 72-lead LFCSP and is ADC features wide bandwidth inputs supporting a variety of specified over the −40°C to +105°C junction temperature range. user-selectable input ranges. An integrated voltage reference This product may be protected by one or more U.S. or eases design considerations. international patents. The analog inputs and clock signals are differential inputs. Each
PRODUCT HIGHLIGHTS
pair of ADC data outputs is internally connected to two DDCs 1. Low power consumption per channel. through a crossbar mux. Each DDC consists of up to five cascaded 2. JESD204B lane rate support up to 15 Gbps. signal processing stages: a 48-bit frequency translator, NCO, 3. Wide full power bandwidth supports IF sampling of signals and up to four half-band decimation filters. up to 1.4 GHz. In addition to the DDC blocks, the AD9694 has several 4. Buffered inputs ease filter design and implementation. functions that simplify the automatic gain control (AGC) 5. Four integrated wideband decimation filters and function in the communications receiver. The programmable numerically controlled oscillator (NCO) blocks supporting threshold detector allows monitoring of the incoming signal multiband receivers. power using the fast detect output bits of the ADC. If the input 6. Programmable fast overrange detection. signal level exceeds the programmable threshold, the fast detect 7. On-chip temperature diode for system thermal management. indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Rev. 0 | Page 3 of 101 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Dither Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C, AND FD_D) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO AND MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS OVERVIEW HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE SETTING UP THE AD9694 DIGITAL INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) JESD204B Tx CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) LATENCY END-TO-END TOTAL LATENCY MULTICHIP SYNCHRONIZATION SYSREF± SET UP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels ADC Pair Addressing Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE SUMMARY MEMORY MAP REGISTER TABLE—DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND PIN 67) OUTLINE DIMENSIONS ORDERING GUIDE