Datasheet AD7172-4 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Low Power, with 4- or 8-channel, 24-bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers |
| Pages / Page | 62 / 5 — AD7172-4. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Test … |
| Revision | B |
| File Format / Size | PDF / 862 Kb |
| Document Language | English |
AD7172-4. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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AD7172-4 Data Sheet SPECIFICATIONS
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, MCLK = internal master clock = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 1.25 31,250 SPS No Missing Codes1 Excluding sinc3 filter ≥ 15 kSPS 24 Bits Resolution See Table 6 and Table 7 Noise See Table 6 and Table 7 ACCURACY Integral Nonlinearity (INL) ±2 ±5.2 ppm of FSR Offset Error2 Internal short ±75 μV Offset Drift Internal short ±230 nV/°C Gain Error2 AVDD1 = 5 V ±5 ±45 ppm of FSR Gain Drift ±0.2 ±0.5 ppm/°C REJECTION Power Supply Rejection AVDD1, AVDD2, VIN = 1 V 98 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz, 60 Hz1 20 Hz output data rate (postfilter), 50 Hz 120 dB ± 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB ANALOG INPUTS Differential Input Range VREF = (REF+) − (REF−) ±VREF V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V Analog Input Current Input Buffers Disabled Input Current ±6 μA/V Input Current Drift ±0.45 nA/V/°C Input Buffers Enabled Input Current ±5.5 nA Input Current Drift ±0.1 nA/°C Crosstalk 1 kHz input −120 dB REFERENCE INPUTS Differential Input Range VREF = (REF+) − (REF−) 1 2.5 AVDD1 V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V REFIN Input Current Input Buffers Disabled Input Current ±9 μA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock ±1 nA/V/°C Input Buffers Enabled Input Current ±100 nA Input Current Drift ±2.5 nA/°C Normal Mode Rejection1 See the Rejection parameter Common-Mode Rejection 95 dB BURNOUT CURRENTS Source/Sink Current Analog input buffers must be enabled ±10 μA Rev. B | Page 4 of 61 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-4 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-4 REFERENCE BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 7 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE
AD7172-4 Data Sheet SPECIFICATIONS
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, MCLK = internal master clock = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 1.25 31,250 SPS No Missing Codes1 Excluding sinc3 filter ≥ 15 kSPS 24 Bits Resolution See Table 6 and Table 7 Noise See Table 6 and Table 7 ACCURACY Integral Nonlinearity (INL) ±2 ±5.2 ppm of FSR Offset Error2 Internal short ±75 μV Offset Drift Internal short ±230 nV/°C Gain Error2 AVDD1 = 5 V ±5 ±45 ppm of FSR Gain Drift ±0.2 ±0.5 ppm/°C REJECTION Power Supply Rejection AVDD1, AVDD2, VIN = 1 V 98 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz, 60 Hz1 20 Hz output data rate (postfilter), 50 Hz 120 dB ± 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB ANALOG INPUTS Differential Input Range VREF = (REF+) − (REF−) ±VREF V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V Analog Input Current Input Buffers Disabled Input Current ±6 μA/V Input Current Drift ±0.45 nA/V/°C Input Buffers Enabled Input Current ±5.5 nA Input Current Drift ±0.1 nA/°C Crosstalk 1 kHz input −120 dB REFERENCE INPUTS Differential Input Range VREF = (REF+) − (REF−) 1 2.5 AVDD1 V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V REFIN Input Current Input Buffers Disabled Input Current ±9 μA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock ±1 nA/V/°C Input Buffers Enabled Input Current ±100 nA Input Current Drift ±2.5 nA/°C Normal Mode Rejection1 See the Rejection parameter Common-Mode Rejection 95 dB BURNOUT CURRENTS Source/Sink Current Analog input buffers must be enabled ±10 μA Rev. B | Page 4 of 61 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-4 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-4 REFERENCE BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 7 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE
