Datasheet AD9656 (Analog Devices) - 8

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Data Sheet AD9656 Parameter1 Temperature Min Typ Max Unit
WORST OTHER SPUR OR HARMONIC (EXCLUDING SECOND OR THIRD) fIN = 9.7 MHz 25°C −95 dBc fIN = 16 MHz 25°C −95 dBc fIN = 64 MHz 25°C −94 dBc fIN = 128 MHz 25°C −89 dBc fIN = 201 MHz 25°C −91 dBc fIN = 301 MHz 25°C −89 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)—INPUT AMPLITUDE = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz 25°C −89 dBc CROSSTALK2 25°C −94 dB CROSSTALK (OVERRANGE CONDITION)3 25°C −89 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is defined as the input being 3 dB above full-scale.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, 2.8 V p-p differential input, 1.4 V reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 5. Parameter1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK±) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage Range2 Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF SYNCINB INPUT (SYNCINB±) Logic Compliance LVDS Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Range Full 0.3 3.6 V p-p Input Voltage Range Full DGND DVDD V Input Common-Mode Voltage Range Full 0.9 1.4 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −5 +5 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ SYSREF INPUT (SYSREF±) Logic Compliance LVDS Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Range Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Voltage Range Full 0.9 1.4 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −5 +5 µA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ LOGIC INPUT (SYNC) Logic 1 Voltage Range Full 1.2 AVDD + 0.2 V Logic 0 Voltage Range Full 0 0.8 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF Rev. A | Page 7 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS, VREF = 1.4 V DC SPECIFICATIONS, VREF = 1.0 V AC SPECIFICATIONS, VREF = 1.4 V AC SPECIFICATIONS, VREF = 1.0 V DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.4 V VREF = 1.0 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common-Mode Voltage Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS JESD204B Transmit Top Level Description JESD204B Overview JESD204B Configurations Initial JESD204B Link Startup Resynchronization JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bit 5—PDWN Pin Function Bit 4—JTX Standby Mode Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bit 2—Chop Mode Output Mode (Register 0x14) Bits[7:5]—JTX CS Mode Bits[1:0]—Output Format Clock Phase Control (Register 0x16) Bits[6:4]—Input Clock Phase Adjust JTX User Pattern (Register 0xA0 to Register 0xA7) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bit 3—VCM Power-Down APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE