Datasheet AD9656 (Analog Devices) - 10

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Data Sheet AD9656 Parameter1, 2 Temperature Min Typ Max Unit
Deterministic Jitter (DJ) At 6.4 Gbps 25°C 8 ps Random Jitter (RJ) At 6.4 Gbps 25°C 1.25 ps rms Output Rise Time/Fall Time 25°C 50 ps Differential Termination Resistance 25°C 100 Ω APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms Out of Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 The clock divider can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 Maximum conversion rate is with the AD9656 not limited by the maximum al owable output data rate. See the Digital Outputs and Timing section for information on conditions when the conversion rate is limited by the maximum allowable output data rate. 5 Refer to Figure 3 for timing diagram. 6 Typical PLL lock time at 125 MSPS (24 μs + 7680 sample clock periods) 7 Time required for the ADC to return to normal operation from power-down mode. 8 Time required for the JESD204B output to return to normal operation from power-down mode at 125 MSPS (PLL lock time + 13 sample clock periods) 9 Delay required for SYNCINB rising edge/Rx CGS start. See Figure 66. 10 ADC conversion rate cycles.
TIMING SPECIFICATIONS Table 7. Parameter Description Limit Unit
SPI TIMING REQUIREMENTS See Figure 74 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the 10 ns min SCLK falling edge (not shown in Figure 74) tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the 10 ns min SCLK rising edge (not shown in Figure 74) Rev. A | Page 9 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS, VREF = 1.4 V DC SPECIFICATIONS, VREF = 1.0 V AC SPECIFICATIONS, VREF = 1.4 V AC SPECIFICATIONS, VREF = 1.0 V DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.4 V VREF = 1.0 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common-Mode Voltage Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS JESD204B Transmit Top Level Description JESD204B Overview JESD204B Configurations Initial JESD204B Link Startup Resynchronization JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bit 5—PDWN Pin Function Bit 4—JTX Standby Mode Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bit 2—Chop Mode Output Mode (Register 0x14) Bits[7:5]—JTX CS Mode Bits[1:0]—Output Format Clock Phase Control (Register 0x16) Bits[6:4]—Input Clock Phase Adjust JTX User Pattern (Register 0xA0 to Register 0xA7) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bit 3—VCM Power-Down APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE